Patents Assigned to Interconnect Technology Inc.
  • Patent number: 8926361
    Abstract: An electrical contact includes a contact body having a mating portion and a barrel portion configured for receiving an electrical conductor. The barrel portion includes a wall defining a bore having a closed end and open end, and the bore includes a core receiver portion for receiving the core of an electrical conductor and a plug receiver portion adjacent the closed end of the bore. A hole is formed in the barrel portion proximate the closed end of the bore and extending into the plug receiver portion of the bore through the wall. A plug has a body portion configured to be inserted into the bore and to engage the plug receiver portion of the bore. The plug is disposed in the end of the plug receiver portion and is further configured to seal the plug receiving portion of the bore and the hole from the rest of the bore.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: January 6, 2015
    Assignee: Carlisle Interconnect Technologies, Inc.
    Inventor: Laudencio Oduca
  • Patent number: 8926366
    Abstract: A board-mount electrical connector includes an electrically conductive rear shell interposed between a contact-retaining front body and an insulator member that holds a plurality of board-mount contacts. The rear shell includes at least one electrically conductive shielding divider that extends through the insulator member and is positioned between two or more of the board-mount contacts. Also disclosed is a rear shell elbow for an electrical connector that is assembled from a pair of slidably interlocking members that form an X-shaped divider within the rear shell when assembled.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: January 6, 2015
    Assignee: Carlisle Interconnect Technologies, Inc.
    Inventor: Phong Dang
  • Patent number: 8870149
    Abstract: A hold-down assembly for retaining a portable electronic unit within an avionics equipment mounting tray includes a shaft, a locking collar, and an actuator knob. The shaft is coupled to pivot with the mounting tray. The locking collar slides along the shaft to engage the portable electronic unit. The actuator knob includes a knob body, a ratchet plate having detent holes within the knob body, a ball bearing, and a compression spring within the knob body. As the actuator knob is rotated to move along the shaft, the knob body and the ball bearing rotate with respect to the ratchet plate, and the ball bearing is forced against a spring bias of the compression spring as the ball bearing travels between adjacent detent holes.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: October 28, 2014
    Assignee: Carlisle Interconnect Technologies, Inc.
    Inventor: Nicholas P. Rodig
  • Publication number: 20140273585
    Abstract: An electrical connector includes an electrically conductive housing for inhibiting electromagnetic interference. A latch device is mounted to opposite sides of the housing and extends from the housing for positively latching together the electrical connector with a mating connector. The latch device includes a biasing member for driving a latching end of the latch device toward a catch of the mating connector to securely retain the connectors in a mated configuration. The housing further includes a skirt on a mating end, the skirt having a plurality of cantilevered tangs for bearing against a corresponding skirt of the mating connector.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 18, 2014
    Applicant: Carlisle Interconnect Technologies, Inc.
    Inventor: Phong Dang
  • Publication number: 20140273669
    Abstract: An electrical contact includes a contact body having a mating portion and a barrel portion configured for receiving an electrical conductor. The barrel portion includes a wall defining a bore having a closed end and open end, and the bore includes a core receiver portion for receiving the core of an electrical conductor and a plug receiver portion adjacent the closed end of the bore. A hole is formed in the barrel portion proximate the closed end of the bore and extending into the plug receiver portion of the bore through the wall. A plug has a body portion configured to be inserted into the bore and to engage the plug receiver portion of the bore. The plug is disposed in the end of the plug receiver portion and is further configured to seal the plug receiving portion of the bore and the hole from the rest of the bore.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: CARLISLE INTERCONNECT TECHNOLOGIES, INC
    Inventor: CARLISLE INTERCONNECT TECHNOLOGIES, INC.
  • Patent number: 8764471
    Abstract: An electrical connector system includes a pin connector and a socket connector that each attach to a cable having multiple twisted pairs of wires. The connectors include features for shielding each pair of pin or socket contacts from the other pairs of pin or socket contacts to reduce interference and crosstalk. A contact-retaining shell of one of the connectors includes an integrally formed insertion plug having cantilever elements that electrically contact a conductive surface of the mating connector to provide a low-impedance pathway between the shell and the mating connector for purposes of grounding and/or shielding. The electrical connector system is designed to be readily disassembled and reassembled for repair or re-work without the use of special tools.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: July 1, 2014
    Assignee: Carlisle Interconnect Technologies, Inc.
    Inventor: Phong Dang
  • Patent number: 8685284
    Abstract: A conducting paste and method of forming the paste for device level interconnection. The conducting paste contains metal loading in the range 80-95% that is useful for making five micron device level interconnects. The conducting paste is made by mixing two different conducting pastes, each paste maintaining its micro level individual rich region in the mixed paste even after final curing. One paste contains at least one low melting point alloy and the other paste contains noble metal fillers such as gold or silver flakes. In general, average flake size below five micron is suitable for five micron interconnects. However, 1 micron or smaller silver flakes and an LMP mixture is preferred for five micron interconnects. The amount of LMP based paste in the final mixture is preferably 20-50% by weight. The nano micro paste embodiment shows good electrical yield (81%) and low contact resistance.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: April 1, 2014
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, Roy H. Magnuson, Mark D. Poliks, Voya R. Markovich
  • Patent number: 8653368
    Abstract: A splicing member for sealing a crimped wire splice sleeve without application of high temperatures or chemical reactions is disclosed. The splicing member includes a cylindrical locking member having one or more lock tabs and/or one or more retaining clips. The lock tabs and/or retaining clips are engaged by the insertion of a crimped wire splice sleeve into the splicing member and lock the crimped wire splice sleeve into the splicing member. A rubber sheath is formed around the cylindrical locking member including sealing sections having parallel circular openings concentric with the outer surface of the sheath. The sealing sections prevent environmental conditions from reaching the crimped wire splice sleeve locked inside the cylindrical locking member. For example, moisture is prevented from reaching the crimped wire splice sleeve.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: February 18, 2014
    Assignee: Carlisle Interconnect Technologies, Inc.
    Inventors: Gregory A. Genco, Laudencio B. Oduca
  • Publication number: 20130344723
    Abstract: A one piece integral electrical terminal has a mount portion and a wire receiving portion. The wire receiving portion has a continuous annular interior wall having a contact portion with an integral oxide breaker especially suited to breaking through the oxide layer on aluminum wire. The wire receiving portion also has a sealing portion with at least one integral seal ring. An electrical cable is made by crimping the electrical terminal to an aluminum wire using a modified hexagonal crimp.
    Type: Application
    Filed: August 26, 2013
    Publication date: December 26, 2013
    Applicant: CARLISLE INTERCONNECT TECHNOLOGIES, INC.
    Inventors: Kenneth J. Peters, William L. Arenburg
  • Patent number: 8607445
    Abstract: A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: December 17, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, Frank D. Egitto, John M. Lauffer, How T. Lin
  • Patent number: 8592299
    Abstract: A structure for minimizing resistance between a semi-insulating x-ray detector crystal and an electrically conducting substrate. Electrical contact pads are disposed on the detector crystal and on the substrate with an electrical interconnect between the contact pads formed from a conductive adhesive and washed solder in electrical and mechanical communication with the pads.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: November 26, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Voya R. Markovich, Rabindra N. Das, Rajinder S. Rai, Michael Vincent
  • Patent number: 8585337
    Abstract: A mechanism for attaching a structure to a relatively flat panel includes a housing containing an outer button which contains an inner button. Displacement of the inner button into the outer button causes a moveable attachment portion to partially collapse toward a centerline which permits the moveable attachment portion to pass through an engagement aperture in the panel. Movement of the outer button into the housing permits the moveable engagement portion to extend past a back surface of the panel to engage the back surface and hold the attaching structure to the panel via forces exerted by biasing members once the buttons are released.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: November 19, 2013
    Assignee: Carlisle Interconnect Technologies, Inc.
    Inventor: Phong Dang
  • Patent number: 8579659
    Abstract: A push-on connector system includes a male push-on bore including a center conductor pin, and a female push-on core including a socket. The male push-on bore receives the female push-on core. A second bore is configured forwardly of the male push-on bore, and a latch track is positioned in the second bore and forms a plurality of inclined latch surfaces. A movable collar is mounted rearwardly of the female push-on core with a plurality of bayonet pins as is configured for engaging the second bore. The bayonet pins slide along the inclined latch surfaces to axially drive the movable collar into the second bore and secure the female push-on core into the male push-on bore. A resilient member is coupled between the movable collar and female push-on core to bias the female push-on core into the male push-on bore.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: November 12, 2013
    Assignee: Carlisle Interconnect Technologies, Inc.
    Inventors: Hau Tran, Mohsin Peeran, Phil Vaccaro
  • Patent number: 8558374
    Abstract: An electronic package with two circuitized substrates which sandwich an interposer therebetween, the interposer electrically interconnecting the substrates while including at least one electrical component (e.g., a power module) substantially therein to provide even further operational capabilities for the resulting package.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: October 15, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Voya R. Markovich, Rabindra N. Das, Frank D. Egitto, James J. McNamara, Jr.
  • Publication number: 20130264669
    Abstract: A method of making a semiconductor radiation detector wherein the metal layers which serve as the cathode and anode electrodes are recessed from the designated prospective dice lines which define the total upper and lower surface areas for each detector such that the dicing blade will not directly engage the metal during dicing and therefore prevent metal from intruding upon (smearing) the vertical side walls of the detector substrate.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 10, 2013
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Handong Li, Michael Prokesch, John Francis Eger
  • Patent number: 8541687
    Abstract: A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: September 24, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Voya Markovich, Timothy Antesberger, Frank D. Egitto, William Wilson, Rabindra N. Das
  • Patent number: 8536459
    Abstract: A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: September 17, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Voya Markovich, Timothy Antesberger, Frank D. Egitto, William Wilson, Rabindra N. Das
  • Patent number: 8519267
    Abstract: A one piece integral electrical terminal has a mount portion and a wire receiving portion. The wire receiving portion has a continuous annular interior wall having a contact portion with an integral oxide breaker especially suited to breaking through the oxide layer on aluminum wire. The wire receiving portion also has a sealing portion with at least one integral seal ring. An electrical cable is made by crimping the electrical terminal to an aluminum wire using a modified hexagonal crimp.
    Type: Grant
    Filed: February 16, 2009
    Date of Patent: August 27, 2013
    Assignee: Carlisle Interconnect Technologies, Inc.
    Inventors: Kenneth J. Peters, William L. Arenburg
  • Patent number: 8499440
    Abstract: A method of making a circuitized substrate including a composite layer having a first dielectric sub-layer including a halogen-free resin and fibers dispersed therein and a second dielectric sub-layer without fibers but also including a halogen-free resin with inorganic particulates therein.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: August 6, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papthomas
  • Patent number: 8501575
    Abstract: Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: August 6, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, Frank D. Egitto, How T. Lin, John M. Lauffer, Voya R. Markovich