Abstract: A method of converting a land grid array (LGA) module to a ball grid array (BGA) module by removing and oxidizing portions of the LGA conductive pad features on the upper surface of the LGA module. A BGA solder ball is deposited on the remaining portion of the conductive feature of the LGA module, with subsequent reflowing of the BGA solder ball. By modifying the LGA module to support a BGA structure, excessive heat generated by components placed on the modified LGA pad can be conducted through the BGA structure and into the element on which the LGA module is attached, such as a PCB.

Abstract: An electrically conductive adhesive (ECA) for repairing electrically conductive pad and trace interconnects and a method of repairing interconnect locations. The method of repairing at least one defect within the area of electrically conductive circuitized substrate traces and pads outside of a pristine center area incorporates an ECA and a forming gas plasma. The ECA contains a mixture of components that allow the adhesive to be adapted to specific requirements. Curing the adhesive results in effective electrical connections being formed between the adhesive and the base pad so that the metallurgies of the conductors and of the ECA are effectively combined to engage and repair the conductor defect.

Abstract: A circuitized substrate for use in such electrical structures as information handling systems wherein the substrate includes a capacitive substrate as part thereof. The capacitive substrate includes a thin film layer of capacitive material strategically positioned on a conductive layer relative to added electrically conductive elements to in turn provide a plurality of internal capacitors within the final circuitized substrate during operation thereof. A method of making such a circuitized substrate is also provided.

Abstract: Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.

Abstract: A method of making a circuitized substrate including a resistor comprised of material which includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ceramic component. The ceramic component may be a ferroelectric ceramic and/or a high surface area ceramic and/or a transparent oxide and/or a dope manganite. Alternatively, the material will include the polymer resin and nano-powders, with the nano-powders comprising at least one metal coated ceramic and/or at least one oxide coated metal component. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) utilizing such a circuitized substrate are also provided.

Abstract: A method of making an electronic package designed for interconnecting high density patterns of conductors of an electronic device (e.g., semiconductor chip) and less dense patterns of conductors of hosting circuitized substrates (e.g., chip carriers, PCBs). In one embodiment, the method includes bonding a chip to a single dielectric layer, forming a high density pattern of conductors on one surface of the layer, forming openings in the layer and then depositing metallurgy to form a desired circuit pattern which is then adapted for engaging and being electrically coupled to a corresponding pattern on yet another hosting substrate. According to another embodiment of the invention, an electronic package using a dual layered interposer is provided. Also provided are methods of making circuitized substrate assemblies using the electronic packages made using the invention's teachings.

Abstract: A method of making a circuitized substrate which involves forming a plurality of individual film resistors having approximate resistance values as part of at least one circuit of the substrate, measuring the resistance of a representative (sample) resistor to define its resistance, utilizing these measurements to determine the corresponding precise width of other, remaining film resistors located in a defined proximity relative to the representative resistor such that these remaining film resistors will include a defined resistance value, and then selectively isolating defined portions of the resistive material of these remaining film resistors while simultaneously defining the precise width of the resistive material in order that these film resistors will possess the defined resistance.

Abstract: A circuitized substrate in which two conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric are smooth (e.g., preferably by chemical processing) and include a thin, organic layer thereon, while the outer surfaces of both foils are also smooth (e.g., preferably also using a chemical processing step). One of these resulting conductive layers may function as a ground or voltage plane while the other may function as a signal plane with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided.

Abstract: An electronic package with two circuitized substrates which sandwich an interposer therebetween, the interposer electrically interconnecting the substrates while including at least one electrical component (e.g., a power module) substantially therein to provide even further operational capabilities for the resulting package.

Abstract: A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.

Abstract: An electronic package with two circuitized substrates which sandwich an interposer therebetween, the interposer electrically interconnecting the substrates and also including an opening therein in which is positioned at least one electrical component, such as a semiconductor chip, coupled to the lower or base substrate. A second component may also be mounted on and electrically coupled to the upper surface of the top or cover circuitized substrate. A method of making such a package is also provided.

Abstract: A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin.

Abstract: A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.

Abstract: A circuitized substrate and method of making same in which quantities of thru-holes are formed within a dielectric interposer layer. The substrate includes two printed circuit board (PCB) layers bonded to opposing sides of the interposer with electrically conductive features of each PCB aligned with the interposer thru-holes. Resistive paste is positioned on the conductive features located adjacent the thru-holes to form controlled electrically resistive connections between conductive features of the two PCBs. A circuitized substrate assembly and method of making same are also disclosed.

Abstract: A method of forming a compressible contact structure on a semi-conductor chip which comprises bonding a compressible polymer layer to the chip's surface, forming a plurality of openings within the layer, depositing electrically conductive material within the openings to form electrical connections with the chip's contacts, forming a plurality of electrically conductive line elements on the polymer layer extending from a respective opening and each including an end portion, and forming a plurality of contact members each on a respective one of the line segment end portions. The compressible polymer layer allows the contact members to deflect toward (compress) the chip when the contact members are engaged by an external force or forces. A semi-conductor chip including such a compressible contact structure is also provided.

Abstract: A power core adapted for use as part of a circuitized substrate, e.g., a PCB or LCC. The core includes a first layer of low expansion dielectric and two added layers of a different low expansion dielectric bonded thereto, with two conductive layers positioned on the two added low expansion dielectric layers. At least one of the conductive layers serves as a power plane for the power core, which in turn is usable within a circuitized substrate, also provided. Methods of making the power core and circuitized substrate are also provided. The use of different low expansion dielectric materials for the power core enables the use of support enhancing fiberglass in one layer while such use is precluded in the other two dielectric layers, thus preventing CAF shorting problems in highly precisely defined thru holes formed within the power core.

Abstract: A spring actuated clamping mechanism has a backer plate with an upper surface and a lower surface. A set of apertures is formed along the periphery of the backer plate. The upper surface of the backer plate has at least one backer plate recess, and preferably four recesses, formed therein. A threaded aperture is also formed in the backer plate. A compression plate is also provided. A second set of apertures is formed along the periphery of the compression plate. The lower surface of the compression plate has at least one compression plate recess, and at least one compression plate aperture. At least one compression spring is disposed between the backer plate and the compression plate. A screw tension release mechanism is screwed into the backer plate threaded aperture and inserted through the compression plate aperture.

Abstract: A high bandwidth semiconductor printed circuit board assembly (PCBA) providing a layer of dielectric substrate containing plated vias with an upper and lower surface plated with etched copper, mated with a second layer of etched copper plated dielectric containing plated vias that is placed on the top surface of the first layer. A third layer of etched copper plated dielectric containing plated vias may be placed on the bottom layer of etched copper foil. A base layer of etched copper plated thick dielectric containing plated vias is laminated simultaneously with the preceding layers to provide the high bandwidth digital and RF section of the assembly.

Abstract: A substrate and method for making same for use in electronic packages having a core layer of copper-invar-copper (CIC) with a layer of polytetrafluoroethylene (PTFE) placed upon both sides of the CIC. A layer of etched copper foil is placed on the outer surface of each PTFE layer. A layer of liquid crystal polymer (LCP) is placed on both layers of etched copper foil. An external layer of etched copper foil is placed on the external surface of the LCP layers.

Abstract: A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser.