Patents Assigned to Komatsu Electronic Metals Co., Ltd.
  • Patent number: 8090544
    Abstract: A method for shortening a waiting time from the setting of a sample in a chamber to the stabilisation of the intensity for a secondary ion for SIMS analysis (mass analysis of the secondary ion) using a raster variation method is provided. By approximating so that the difference between time-lapse variations in intensities of the secondary ions sequentially measured for irradiation densities of two different primary ions becomes constant, a method capable of carrying out an accurate measurement of the concentration of an impurity in consideration of background noise despite time-lapse variations in the intensities of the secondary ions is provided.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: January 3, 2012
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Kiyoshi Nagai, Tetsuo Ishida
  • Publication number: 20090198452
    Abstract: A method for shortening a waiting time from the setting of a sample in a chamber to the stabilisation of the intensity for a secondary ion for SIMS analysis (mass analysis of the secondary ion) using a raster variation method is provided. By approximating so that the difference between time-lapse variations in intensities of the secondary ions sequentially measured for irradiation densities of two different primary ions becomes constant, a method capable of carrying out an accurate measurement of the concentration of an impurity in consideration of background noise despite time-lapse variations in the intensities of the secondary ions is provided.
    Type: Application
    Filed: June 2, 2005
    Publication date: August 6, 2009
    Applicant: KOMATSU ELECTRONIC METALS CO., LTD.
    Inventors: Kiyoshi Nagai, Tetsuo Ishida
  • Publication number: 20090040512
    Abstract: The surface of an epitaxial wafer is inspected using an optical scattering method. The intensities of light scattered with a narrow scattering angle and light scattered with, a wide scattering angle reflected from laser light scatterers (LLS) on the wafer surface are detected. If the intensifies of narrowly and widely scattered lights are within a prescribed sizing range, it is judged whether the laser light scatterer is a particle or killer defect by deciding into which zone (410, 414, 418, 439) within the sizing range the PLS size based on the narrowly scattered light intensity and the PLS size based, on the widely scattered light intensity fall. If the intensity of the narrowly or widely scattered light exceeds the sizing range (417, 420, 421, 423, 424, 425), or if a plenty of laser light scatterers are continuous or concentrated (422), the laser light scatterers are judged to be killer defects.
    Type: Application
    Filed: September 14, 2006
    Publication date: February 12, 2009
    Applicant: Komatsu Electronic Metals Co., Ltd.
    Inventors: Fumi Nabeshima, Kazuya Togashi, Hiroshi Jiken, Yoshinori Suenaga
  • Publication number: 20070252239
    Abstract: A method is provided capable of universally controlling the proximity gettering structure, the need for which can vary from manufacturer to manufacturer, by arbitrarily controlling an M-shaped distribution in a depth direction of a wafer BMD density after RTA in a nitrogen-containing atmosphere. The heat-treatment method is provided for forming a desired internal defect density distribution by controlling a nitrogen concentration distribution in a depth direction of the silicon wafer for heat-treatment, the method including heat-treating a predetermined silicon wafer used for manufacturing a silicon wafer having a denuded zone in the vicinity of the surface thereof.
    Type: Application
    Filed: April 22, 2005
    Publication date: November 1, 2007
    Applicant: KOMATSU ELECTRONIC METALS CO., LTD.
    Inventors: Susumu Maeda, Takahisa Sugiman, Shinya Sadohara, Shiro Yoshino, Kouzo Nakamura
  • Publication number: 20070229815
    Abstract: A semiconductor wafer surface inspection apparatus detects LADs (Large Area Defects) which are flat and have low heights and differentiates them from particles. This inspection apparatus irradiates each point on the surface of a semiconductor wafer 200 with two parallel laser beams perpendicularly to the points while scanning the surface, and by measuring the phase difference between the two reflected beams, detects points 400 at which an upward inclination exists and points 402 at which a downward inclination exists on the surface of the wafer 200. Areas 404 in which pairs or sets of upward-inclination points 400 and downward-inclination points 402 exist within a prescribed range of mutual distances are inferred to be LADs.
    Type: Application
    Filed: June 1, 2005
    Publication date: October 4, 2007
    Applicant: Komatsu Electronic Metals Co., Ltd.
    Inventors: Fumi Nabeshima, Kazuya Togashi
  • Publication number: 20070218570
    Abstract: An epitaxial wafer and a high-temperature heat treatment wafer having an excellent gettering capability are obtained by performing epitaxial growth or a high-temperature heat treatment. A relational equation relating the density to the radius of an oxygen precipitate introduced in a silicon crystal doped with nitrogen at the time of crystal growth can be derived from the nitrogen concentration and the cooling rate around 1100° C. during crystal growth, and the oxygen precipitate density to be obtained after a heat treatment can be predicted from the derived relational equation relating the oxygen precipitate density to the radius, the oxygen concentration, and the wafer heat treatment process. Also, an epitaxially grown wafer and a high-temperature annealed wafer whose oxygen precipitate density has been controlled to an appropriate density are obtained, using conditions predicted by the method.
    Type: Application
    Filed: August 11, 2005
    Publication date: September 20, 2007
    Applicant: KOMATSU ELECTRONIC METALS CO., LTD
    Inventors: Kouzo Nakamura, Susumu Maeda, Kouichirou Hayashida, Takahisa Sugiman, Katsuhiko Sugisawa
  • Publication number: 20070059935
    Abstract: A polishing method includes a slurry adjusting step for adjusting a polishing slurry containing silica particles so that the number of silica particles having a composition ratio of Si/O of 50-60 wt %/40-50 wt %, a modulus of elasticity of 1.4×1010 Pa or higher and a particle size of 1 ?m or larger is 3000 pcs/ml or less. A semiconductor wafer is polished using the polishing slurry adjusted in the slurry adjusting step.
    Type: Application
    Filed: August 30, 2006
    Publication date: March 15, 2007
    Applicant: KOMATSU ELECTRONIC METALS CO., LTD.
    Inventors: Kazuaki Kozasa, Motoharu Yamada, Uasuhiro Tomita, Hiromi Wakabayashi
  • Patent number: 7141992
    Abstract: There is provided a method for calculating a more accurate metal impurity concentration contained in a silicon wafer by correcting measured values with a calibration based on a dependent relationship of the minority carrier diffusion length with a period of time elapsing from the activation to the actual measurement, an electric resistivity, and a temperature if there is such a relationship, in the measurement of the metal impurity concentration by utilizing the surface photovoltage. In the calibration step, such dependent relationship may be obtained by utilizing the metal impurity concentration measured by methods of different principles and actually measured values are corrected in light of the dependent relationship in the measuring step such that the metal impurity concentration is measured more accurately.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: November 28, 2006
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Ryuuji Ohno, Kei Matsumoto
  • Patent number: 6877668
    Abstract: A plurality of minute ID marks are inscribed on a semiconductor wafer which is under manufacture, without imposing adverse effect to the wafer, in order to make the marks less susceptible to surface treatment to be performed during the course of manufacture. Further, the minute ID marks act as mutual backups. Inscribing such minute ID marks on a semiconductor wafer prevents confusion due to effacement of ultra-minute marks and eliminates worry about the impossibility of tracing a semiconductor wafer.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: April 12, 2005
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventor: Satoshi Kitagawa
  • Patent number: 6858076
    Abstract: There are provided a system for manufacturing a single-crystal ingot which is equipped with a cooler for cooling the single-crystal ingot being pulled and is capable of forming a tail without involvement of excessive heating of a crucible, as well as to a method for controlling the system. In a system for manufacturing a single-crystal ingot having a cooler for cooling a single-crystal ingot which is being pulled from molten raw material (called a single-crystal pulled ingot), when a tail of the single-crystal pulled ingot is formed, the cooler is moved away from the solid/melt interface between the single-crystal ingot and the molten raw material, to thereby reduce the power dissipated by the system. In the system, the cooler is moved upward after the end of a product area of the single-crystal ingot has been cooled until it passes through a grown-in defect temperature range.
    Type: Grant
    Filed: May 10, 2000
    Date of Patent: February 22, 2005
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hirotaka Nakajima, Toshirou Kotooka, Yoshiyuki Shimanuki, Hiroshi Inagaki, Shigeki Kawashima, Makoto Kamogawa
  • Patent number: 6777820
    Abstract: To provide a semiconductor wafer having dot marks produced by irradiating laser beam capable of selecting a marking region capable of reading and writing marks in a state in which the marks hardly vanish and the semiconductor wafer is contained in a wafer cassette, inscribing information of an identification number or electric properties in the region and grasping past history by a unit of the wafer in processing steps or semiconductor fabrication steps thereafter, a very small dot mark is formed by irradiating laser having a diameter of 1 through 13 &mgr;m on an inner wall face of a notch (1) formed on an outer peripheral face of a semiconductor wafer (W), particularly on an inclined face of its peripheral edge.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: August 17, 2004
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Teiichirou Chiba, Etsurou Satou, Jun Tajika
  • Patent number: 6517667
    Abstract: An polishing apparatus consists of a piston which is fixed to the rotation axis, a ceramic plate which is oppositely arranged against the piston via a silicone gel, and a cylinder which houses these components. The wafer is attached on the bottom surface of a backing pad, and will be pressed and rotated by the piston in order to polish the surface thereof.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: February 11, 2003
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventor: Yuichi Nakayoshi
  • Patent number: 6495465
    Abstract: The present invention provides a method for appraising the condition of a polishing cloth, and a method for manufacturing semiconductor wafers employing the disclosed appraisal method, allowing acceptably low light point defect numbers of semiconductor wafers to be maintained. The disclosed method comprises polishing the semiconductor wafer using a polishing cloth, washing the wafer, and drying the wafer. The size of particles comprising light point defects is chosen, and the number of light point defects on the semiconductor wafer is counted. Typically, the diameter of particles comprising light point defects is set as 0.12 &mgr;m or greater. The polishing cloth is exchanged when the number of light point defects counted exceeds a prescribed number.
    Type: Grant
    Filed: March 10, 1999
    Date of Patent: December 17, 2002
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Yuichi Nakayoshi, Naoki Yamada
  • Patent number: 6315827
    Abstract: There is described an apparatus for producing a single crystal ingot capable of stably manufacturing a single crystal ingot by means of the Czochralski method, without being affected by influence of variation in extension of wires or an offset in points clamped by a clamping member. The clamping member is engaged with an engagement step formed in a single crystal which is being pulled by the CZ method, and the single crystal is pulled. The single crystal ingot manufacturing apparatus is provided with a flexible mechanism for absorbing variation in extension of the wires, in intermediate portions of the wires. Variation in extension of the wires is eliminated by means of the flexible mechanism, thereby retaining the single crystal in an upright position. Further, a sacrifice member which deforms so as to conform to the circumference of the engagement step is interposed between the clamping member and the engagement step, thereby preventing occurrence of cracking or deformation in the single crystal.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: November 13, 2001
    Assignee: Komatsu Electronics Metals Co., Ltd.
    Inventors: Shoei Kurosaka, Junsuke Tomioka, Masakazu Kobayashi, Kazuhiro Mimura, Kenji Okamura, Hiroshi Monden, Naritoshi Ohtsukasa, Hiroshi Yoshinada
  • Patent number: 6273944
    Abstract: In growing silicon single crystals by the CZ method, the cooling rate in the 1150-1080° C. temperature zone (defect-forming temperature range) where the grown-in defects are formed is set at more than 2.0° C./min to manufacture single crystals having an as-grown LSTD density of larger than 3.0×106/cm3 or a FPD density of larger than 6.0×105/cm3. As this single crystal has a small defect size, thus the dissolution rate of the defects increases by the heat treatment in a non-oxidizing atmosphere containing a hydrogen gas, so the effect of the hydrogen heat treatment can extend to the depth more than 3 &mgr;m from the wafer surface.
    Type: Grant
    Filed: April 6, 2000
    Date of Patent: August 14, 2001
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Toshiaki Saishoji, Kozo Nakamura, Junsuke Tomioka
  • Patent number: 6270575
    Abstract: A value of electric current flowing a neck to a melt is detected, and it is judged that a breaking of the neck occurs when the detected value has been zero, and then a seed is lowered to dip a broken part on the melt. After that the seed is lifted again to restart a pulling operation.
    Type: Grant
    Filed: June 21, 1999
    Date of Patent: August 7, 2001
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Shoei Kurosaka, Makoto Kamogawa, Nobuyuki Hukuda, Junsuke Tomioka
  • Patent number: 6245678
    Abstract: A Bernoulli type chucking device 2 supports the rear surface 12 of a semiconductor wafer 1. The etchant 30 turns around and reaches the portion beneath the beveled portion 13 of the semiconductor wafers 1. However, the etchant is restrained on the beveled portion by a gas flow coming from the openings 22A of the gas-expelling passages 22 in the centrifugal direction. The gas belows off the etchant, which has turned around and is going to reach the rear surface. Thus, the beveled portion 13 is mirror-finished when etching of the semiconductor wafer front surface 11 is carried out, and mirror-finishing of part of the rear surface 12 can be avoided. Furthermore, mirror-finishing can be performed without being influenced by the shape of the beveled portions of semiconductor wafers. Compared with conventional method, this invention can perform mirror-finishing more efficiently.
    Type: Grant
    Filed: January 7, 1999
    Date of Patent: June 12, 2001
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hiroaki Yamamoto, Akihiro Ishii
  • Patent number: 6234873
    Abstract: A method for manufacturing semiconductor wafers is provided. According to this invention, wafers are obtained by slicing a single-crystal semiconductor ingot. The sliced wafers are beveled at their peripheral rims. The beveled wafers are flattened by a lapping process. The front and the rear surfaces of the flattened wafers are spin-etched with an acid etchant liquid. The glossiness of the rear surfaces of the spin-etched wafers is controlled to a value of 130-300 %. The front surfaces of the wafers whose rear surfaces have been spin-etched are polished, thereby obtaining mirror-polished surfaces. The front surfaces may also be spin-etched prior to polishing.
    Type: Grant
    Filed: October 28, 1998
    Date of Patent: May 22, 2001
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hiroaki Yamamoto, Akihiro Ishii, Kouichi Imura
  • Patent number: 6217650
    Abstract: In an epitaxial-wafer fabricating process for epitaxially growing a silicon layer on the surface of a silicon wafer having the crystal orientation <100> or <111> and an inclination angle of 0°±1° in a reactive gas at a atmosphereicpressure, a growth temperature T is lower than a normal growth temperature by 50° C. to 100° C. during the process of epitaxial growth.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: April 17, 2001
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Takeshi Hirose, Hiroyuki Kawahara, Takeo Tamura, Masayoshi Danbata
  • Patent number: 6179910
    Abstract: This invention provides a method for manufacturing silicon single crystals. The method is capable of eliminating void defects existing in deep regions of a silicon single crystal despite the size of the silicon single crystal. The silicon single crystals according to this invention are pulled the radius of a ring-shaped oxidation induced stacking fault (OSF ring) of a wafer is larger than half the radius of the wafer during the process of thermal oxidation treatment.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: January 30, 2001
    Assignee: Komatsu Electronic Metals Co., LTD
    Inventors: Takashi Yokoyama, Shin Matsukuma, Toshiaki Saishoji, Kozo Nakamura, Junsuke Tomioka