Patents Assigned to Komatsu Electronic Metals Co., Ltd.
  • Patent number: 5943549
    Abstract: The method of evaluating silicon wafers according to this invention is capable of predicating degradation of the quality of oxide film insulation, which is incurred, on the silicon wafers, by process faults or local residual strains undetectable by the naked eye. The method includes the following steps of: removing selectively a surface of a silicon wafer treated by mirror polishing by using an etching selectivity caused by an unordinary surface state; counting the number of etch pits on the surface of the silicon wafer with the aid of an optical microscope; and judging the quality of the silicon wafer based on the etch pit density, which is calculated from the above number of etch pits, and the threshold value of etch pit density. The threshold value of etch pit density of the silicon wafer treated by selective etching is set to be below 5.times.10.sup.5 pits/cm.sup.2, and improvements to the processing of production lines relating to low-quality silicon wafers can be made.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: August 24, 1999
    Assignee: Komatsu Electronics Metals Co., Ltd.
    Inventors: Hisami Motoura, Kouichirou Hayashida
  • Patent number: 5938843
    Abstract: This invention provides a apparatus for pulling up crystal bodies, which is capable of firmly clamping and safely pulling up large-diameter crystal bodies regardless of the location of the necked portions formed on the top of the crystal bodies. A large-diameter portion 52 and a necked portion 51 are formed on the top of the crystal body 5. The swaying members 12 of the necked-portion clamp 1 are capable of swaying upward and downward without restraint. The stopper 14 restrains the swaying members 12 to sway below the horizontal plane on which the swaying members 12a are located. The large-diameter portion 52 can pass through the clamp body 11 by lowering the necked-portion clamp 1 to sway the swaying members 12 upward. The swaying members 12 close to clamp the necked portion 51 when the necked-portion clamp 1 reaches a location near the necked portion 51. The distance between the necked-portion clamp 1 and the seed-crystal 3 is adjustable.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: August 17, 1999
    Assignee: Komatsu Electronic Metals Co.,Ltd.
    Inventors: Yoshinobu Hiraishi, Mitsunori Kawabata, Shoei Kurosaka, Hiroshi Inagaki
  • Patent number: 5938836
    Abstract: This invention provides an apparatus and a method for manufacturing semiconductor single crystals, which enable a steady process of pulling up high-quality single silicon crystals to be easily performed during the growing of silicon single crystals by the CZ method aided by applying a Cusp magnetic field. Three facing homopolar magnets (hereinafter referred to as magnet) 1, 2, and 3 arc disposed outside the single-crystal pulling up chamber. The magnet 3 is located at the same height as the free surface of the melt 6 stored in a quartz crucible as the free surface of the melt 6 stored in a quartz crucible 5. Furthermore, the strength of the magnets 3 is set to be weaker than that of the magnets 1 and 2. The flux lines of the magnets 3 substantially pass through the quartz crucible 5 in the horizontal direction. However, the flux lines of the magnet 3 do not reach the silicon single crystal 7 being pulled up.
    Type: Grant
    Filed: October 23, 1997
    Date of Patent: August 17, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Junsuke Tomioka, Hiroshi Inagaki, Katsura Yamamoto
  • Patent number: 5935325
    Abstract: A weight control in diameter method by using a load cell is applied to a wire-single crystal silicon pulling mechanism, such that the weight of single crystal silicon can be correctly measured, thereby obtaining superior control in diameter and reducing the cost of manufacturing the single crystal silicon.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: August 10, 1999
    Assignee: Komatsu Electronic Metals, Co., Ltd.
    Inventors: Hideki Tsuji, Mitsunori Kawabata, Yoshinobu Hiraishi, Ryo Yamagishi
  • Patent number: 5935322
    Abstract: In the process of forming-the shoulder in which the diameter of a crystal is gradually extended from a small seed crystal to a predetermined value, the largest width of a bright ring, which is formed in a boundary between the melt and the crystal pulled up from the melt, is measured, and an arc width of an arbitrary portion of the bright ring located before the largest width portion is measured. When the largest width of the bright ring has reached a predetermined value, a measured value of the arc width at the arbitrary position of the bright ring is used as a reference value, and after that, automatic control is conducted so that the measured value of the arc width can be close to the reference value.
    Type: Grant
    Filed: April 15, 1998
    Date of Patent: August 10, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Koichi Shimomura, Yoshinobu Hiraishi, Mitsunori Kawabata, Kentaro Nakamura
  • Patent number: 5935326
    Abstract: An cylindrical after-heater surrounding a single crystal being lifted and a cylindrical heat-retaining cylinder installed between the after-heater and the single crystal are provided above a reversed frustrated heat-shielding sleeve disposed near the melted liquid. The heat history of the single crystal can be controlled by adjusting the output of the after-heater and the location of the heat-retaining cylinder. By such an arrangement, rapid respond to the change of the heat environment in a furnace can be made and control of the temperature gradient of the single crystal can be achieved. The single crystal, throughout the whole length, is maintained in the range of from 1000.degree. C. to 1200.degree. C. for more than one hour during lifting operation.
    Type: Grant
    Filed: November 21, 1997
    Date of Patent: August 10, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Toshirou Kotooka, Toshimichi Kubota, Makoto Kamogawa, Yoshiyuki Shimanuki
  • Patent number: 5932048
    Abstract: A method of direct-bonding semiconductor wafers limits the time interval between a bonding step and a bonding anneal step or performs a baking step between the bonding and bonding anneal steps at a predetermined temperature for a predetermined time interval to prevent the formulation of voids on the edge regions of the wafers. The method for fabricating laminated semiconductor wafers includes a bonding step to fit together two polished semiconductor wafers by bonding jigs, and a succeeding bonding anneal step to laminate the wafers. In the method the bonding anneal step is preferably carried out within an hour following the bonding step; or a baking step at a predetermined temperature for a predetermined time interval is carried out between the bonding step and the bonding anneal step. Further, the method can prevent heavy metal impurities attached to the surface of the wafer from diffusing into the wafer by baking the wafer for over 5 minutes at above 100.degree. C.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: August 3, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hiroshi Furukawa, Hirotaka Kato, Hiroaki Yamamoto, Kazuaki Fujimoto
  • Patent number: 5932008
    Abstract: In this invention, three equally spaced and "L" shaped hooks 6B are rotatably supported on the upper peripheral wall of the body 6A of the seed holder 6 at pivots 6E. A radiation screen 7 is hung at the front ends of the hooks 6B via three engaging fixtures 6C affixed on its upper rim. The radiation screen 7 shaped like a hollow trancated cone, is used to surround the lower end of the single-crystal being lifted from the quartz crucible 3 which is disposed within the main chamber 1. According to the apparatus for manufacturing a single-crystal which can perform the descending or ascending movements of the radiation screen, the setting operation, and the lifting operation consecutively and automatically. Therefor the apparatus can enhance the productivity and avoid any problems with process automation, furthermore, it is compatible with conventional equipment.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: August 3, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Yoshinobu Hiraishi, Koichi Shimomura
  • Patent number: 5928422
    Abstract: Regulating cylinder unit is divided into three parts, a third regulating cylinder shaped essentially like a cylinder and installed on the protection cylinder; a first regulating cylinder and a second regulating cylinder which are shaped like reversed truncated cones with different diameters and are capable of engaging with the third regulating cylinder. In addition, the second and third regulating cylinders are brought together in a preset ordering, that is, a flange formed at the outer peripheral rim of the upper end of the second regulating cylinder is engaged with a stepped portion of the third regulating cylinder, and a flange formed at the outer peripheral rim of the upper end of the first regulating cylinder is engaged with a flange formed at the inner peripheral rim of the lower end of the second regulating cylinder.
    Type: Grant
    Filed: March 9, 1998
    Date of Patent: July 27, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Teruhiko Uchiyama, Yoshiyuki Suzuki, Kazuyoshi Date
  • Patent number: 5924916
    Abstract: An apparatus for polishing semiconductor wafers is provided which is capable of efficiently polishing the semiconductor wafers one-by-one by a multi-step polishing, capable of preventing occurrence of spots and scratches due to attachment and detachment to and from top rings, and capable of polishing the semiconductor wafers with high-flatness surfaces. The polish apparatus includes a plurality of holding shafts for holding the semiconductor wafers, a polish table on which the semiconductor wafers are placed and polished, and means for upwardly and downwardly moving the semiconductor wafers which are held by the holding shafts, in which the upward and downward movement of the holding shafts and the attachment and detachment of the semiconductor wafers to and from the holding shafts are independently carried out for each of the holding shafts.
    Type: Grant
    Filed: December 23, 1996
    Date of Patent: July 20, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventor: Junichi Yamashita
  • Patent number: 5925185
    Abstract: A method for fabricating a semiconductor single crystal by the MCZ method by which it is possible to pull large diameter and heavy semiconductor single crystals without breaking the contraction portion, is provided.In the contracting step, change the shape of the crystal growth interface by making the range of the temperature fluctuation caused by convection in the vicinity of the melt surface more than 5.degree. C. so as to eliminate the dislocation in the contracted portion. When a transverse magnetic field is applied by magnets 6,6, the magnetic field intensity is set below 2000 Gauss to properly change the shape of the crystal growth interface to form the contracted portion 10. Thus,even though the diameter of the contracted portion 10 is larger than normal, free dislocation is achieved. After the dislocation is eliminated, the magnetic field intensity is recovered and shoulder 11 is formed.
    Type: Grant
    Filed: June 19, 1997
    Date of Patent: July 20, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Shigeki Kawashima, Hiroshi Inagaki, Hirotaka Nakajima
  • Patent number: 5922137
    Abstract: A method of producing a semiconductor wafer in which a semiconductor wafer cut by a wire saw can be cleaned efficiently and in automatic steps and abrasive grains are substantially completely removed away, and a cleaning apparatus for the method are provided. A semiconductor ingot is cut by a wire saw into cut semiconductor wafers. Each of the cut semiconductor wafers is degrease-cleaned, the semiconductor wafer which has been degrease-cleaned is oil-water separation-cleaned, the semiconductor wafer which has been oil-water separation-cleaned is rinsed, abrasive grains are removed away from the surface of the semiconductor wafer which has been rinse-cleaned, by alkali cleaning, the semiconductor wafer which has been abrasive grain removal-cleaned is separated from a slicing plate.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: July 13, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hisaya Fukunaga, Katsutoshi Kurogi
  • Patent number: 5922213
    Abstract: The mirror-finished silicon surface is brought for pre-processing into contact with the hydrofluoric acid solution, it is NH cleansed, and then it is filmed by oxidation. Otherwise, the silicon surface not mirror-finished is brought for pre-processing into contact with the hydrofluoric acid solution, it is subject to an alkali etching {by a solution of KOH:H.sub.2 O base, NaOH:H.sub.2 O base, NH.sub.4 OH:H.sub.2 O base, or ?NH.sub.2 (CH.sub.2).sub.2 NH.sub.2 !:H.sub.2 O:?C.sub.6 H.sub.4 (OH).sub.2 !base}, it is NH cleansed by the solution of (NH.sub.4 OH:H.sub.2 O.sub.2 base or NH.sub.4 OH:H.sub.2 O.sub.2 :H.sub.2 O base), and then it is filmed by oxidation. In such manufacturing methods the ornamental silicon articles may be processed to their final shape thereafter effecting an oxidation filming. Thus, without using a coloring agent the silicon surface is colored to provide ornamental silicon articles having excellent ornamental properties.
    Type: Grant
    Filed: January 22, 1997
    Date of Patent: July 13, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hideo Kumagai, Kenzo Fujinuki, Itaru Imai
  • Patent number: 5918136
    Abstract: A method of producing an SOI substrate having a single-crystal silicon layer on a buried oxide layer in an electrically insulating state from the substrate by implanting oxygen ions into a single crystal silicon substrate and practicing an anneal processing in an inert gas atmosphere at high temperatures to form the buried oxide layer. After the anneal processing in which the thickness of the buried oxide layer becomes a theoretical value in conformity with the thickness of the buried oxide layer formed by the implanted oxygen, the oxidation processing of the substrate is carried out in a high temperature oxygen atmosphere.
    Type: Grant
    Filed: August 19, 1997
    Date of Patent: June 29, 1999
    Assignees: Komatsu Electronic Metals Co., Ltd.,, Nippon Telegraph and Telephone Corporation, NTT Electronics Technology Corporation
    Inventors: Sadao Nakashima, Katsutoshi Izumi, Norihiko Ohwada, Tatsuhiko Katayama
  • Patent number: 5911826
    Abstract: An electrode is disposed at the lower end of a radiation screen. The electrode is made of single-crystal silicon. A circuit including a power source is established by contacting the electrode and the seed crystal to a silicon melt.
    Type: Grant
    Filed: June 19, 1998
    Date of Patent: June 15, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Yoshinobu Hiraishi, Masafumi Ura
  • Patent number: 5911326
    Abstract: The object of the present invention is to provide a tray for inspecting the surfaces of semiconductor wafers, which can enhance the success at visually identifying flaws on the edge of the semiconductor wafer and can reduce the irregular reflection occurring in the tray. According to this invention, the tray for inspecting the surfaces of semiconductor wafers of this invention includes a panel-shaped tray body 1; and a support frame 3 installed on the surface of the tray body vertically, capable of loading a semiconductor wafer 5 in a manner elevated from and parallel with the tray body 1.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: June 15, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventor: Hiroshi Ikeda
  • Patent number: 5911257
    Abstract: A device for removing objects adhered to a plate for bonding a semiconductor wafer, which can efficiently and completely remove the objects adhered on the chamfered portion of the bonding plate. The rotating shaft 12 of the head for removing adhered objects from the peripheral surface is inclinatorily mounted with respect to the top surface 52 of the bonding plate 5. The peripheral chamfered portion 51 is not aligned with the extended line of the central line 12c of the rotating shaft 12. The upper peripheral surface 21a of the outer tip 21 of the chuck 2 is inclinatorily mounted.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: June 15, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Osamu Morikawa, Kiyoharu Miyakawa
  • Patent number: 5911823
    Abstract: A method for pulling a <110> single-crystal silicon aims at preventing the crystal from being cut in diameter-reducing and suppress the increase in cost due to the cut prevention to the minimum. In the step for forming a diameter-reduced portion performed prior to the step for growing a <110> single-crystal silicon by the Czochralski method, a magnetic field having a strength of 500 gauss or more is applied and while suppressing a melt surface vibration and temperature variation, the crystal diameter is reduced to 2.00 mm or smaller.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: June 15, 1999
    Assignee: Komatsu Electronics Metals Co., Ltd.
    Inventors: Kouji Sonoda, Toshio Mimura
  • Patent number: 5908246
    Abstract: An unsealing structure for packing films that are difficult to rip to pack merchandise is disclosed, where the films can be easily ripped by stripping a tag label. A tearing line 2 is formed in the surface of the film 1 of the film package by hot shearing. A cutout 3 communicates with the tearing line 2 to assist in unsealing the film package. A tag label 4 is affixed to the film 1 and covers the tearing line 2 and the cutout 3.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: June 1, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Yoshiharu Arimura, Youichi Sakurai
  • Patent number: 5908042
    Abstract: A basket for cleaning semiconductor wafers is provided which can catch semiconductor wafers or semiconductor pieces slipping off from a slicing plate so as to prevent them from dropping, and which can hold semiconductor wafers even after the wafers are separated from the slicing plate in a cleaning step.The basket for cleaning semiconductor wafers, includes:at least two upstanding side walls on which ends of a slicing plate are to be respectively placed; at least two side holding rods which are substantially horizontally disposed between side portions of the sidewalls 21, 22, the side holding rods 31, 32 being separated from each other by a distance which is slightly larger than diameters of semiconductor wafers to be housed in the basket; a bottom plate which is formed between lower portions of the side walls; and two clamping rods which are horizontally movable along the side holding rods, thereby the semiconductor wafers sliced on the slicing plate are clamped by moving the clamping rods 51, 52.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: June 1, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hisaya Fukunaga, Katsutoshi Kurogi