Patents Assigned to Kovio, Inc.
  • Patent number: 7956425
    Abstract: Thin film transistors (TFT) and methods for making same. The TFTs generally comprise: (a) a semiconductor layer comprising source and drain terminals and a channel region therebetween; (b) a gate electrode comprising a gate and a gate dielectric layer between the gate and the channel region; (c) a first dielectric layer adjacent to the gate electrode and in contact with the source and drain terminals, the first dielectric layer comprising a material which comprises a dopant therein; and (d) an electrically functional source/drain extensions in the channel region, adjacent to the source and drain terminals, comprising a material which comprises the same dopant as the first dielectric layer.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: June 7, 2011
    Assignee: Kovio, Inc.
    Inventor: James Montague Cleeves
  • Patent number: 7951892
    Abstract: Doped polysilanes, inks containing the same, and methods for their preparation and use are disclosed. The doped polysilane generally has the formula H-[AaHb(DRx)m]q-[(AcHdR1e)n]p—H, where each instance of A is independently Si or Ge, and D is B, P, As or Sb. In preferred embodiments, R is H, -AfHf+1R2f, alkyl, aryl or substituted aryl, and R1 is independently H, halogen, aryl or substituted aryl. In one aspect, the method of making a doped poly(aryl)silane generally includes the steps of combining a doped silane of the formula AaHb+2(DRx)m (optionally further including a silane of the formula AcHd+2R1e) with a catalyst of the formula R4wR5yMXz (or an immobilized derivative thereof) to form a doped poly(aryl)silane, then removing the metal M. In another aspect, the method of making a doped polysilane includes the steps of halogenating a doped polyarylsilane, and reducing the doped halopolysilane with a metal hydride to form the doped polysilane.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: May 31, 2011
    Assignee: Kovio, Inc.
    Inventors: Wenzhuo Guo, Vladimir K. Dioumaev, Joerg Rockenberger
  • Patent number: 7943721
    Abstract: Methods are disclosed of making linear and cross-linked, HMW (high molecular weight) polysilanes and polygermanes, polyperhydrosilanes and polyperhydrogermanes, functional liquids containing the same, and methods of using the liquids in a range of desirable applications. The silane and germane polymers are generally composed of chains of Si and/or Ge substituted with R? substituents, where each instance of R? is, for example, independently hydrogen, halogen, alkenyl, alkynyl, hydrocarbyl, aromatic hydrocarbyl, heterocyclic aromatic hydrocarbyl, SiR?3, GeR?3, PR?2, OR?, NR?2, or SR?; where each instance of R? is independently hydrogen or hydrocarbyl. The cross-linked polymers can be synthesized by dehalogenative coupling or dehydrocoupling. The linear polymers can be synthesized by ring-opening polymerization. The polymers can be further modified by halogenation and/or reaction with the source of hydride to furnish perhydrosilane and perhydrogermane polymers, which are used in liquid ink formulations.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: May 17, 2011
    Assignee: Kovio, Inc.
    Inventor: Vladimir K. Dioumaev
  • Patent number: 7940073
    Abstract: Integrated circuits and methods of permanently disabling integrated circuits are disclosed. An integrated circuit having an erasable non-volatile memory adapted to store an activation code and logic to disable the integrated circuit when the code in the erasable non-volatile memory has been altered or erased after it has been separated from a substrate, is placed into an electromagnetic field of sufficient power to erase or reprogram the erasable non-volatile memory. The entire integrated circuit is permanently disabled by erasing, altering, or reprogramming the erasable non-volatile memory. In preferred embodiments, the integrated circuit comprises a non-erasable non-volatile memory storing the activation code, and circuitry adapted to permanently disable the integrated circuit when the code in the erasable non-volatile memory does not match the activation code in the non-erasable non-volatile memory.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: May 10, 2011
    Assignee: Kovio, Inc.
    Inventor: Roger G. Stewart
  • Patent number: 7932537
    Abstract: Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (Vt) of a diode manufactured using printing or laser writing techniques. The present invention advantageously utilizes the separation between the Vt of an NMOS TFT (Vtn) and the Vt of a PMOS TFT (Vtp) to establish and/or improve stability of a forward voltage drop across a printed or laser-written diode. Further applications of the present invention relate to reference voltage generators, voltage clamp circuits, methods of controlling voltages on related or differential signal transmission lines, and RFID and EAS tags and sensors.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: April 26, 2011
    Assignee: Kovio, Inc.
    Inventors: Vivek Subramanian, Patrick Smith
  • Patent number: 7879696
    Abstract: Compositions, inks and methods for forming a patterned silicon-containing film and patterned structures including such a film. The composition generally includes (a) passivated semiconductor nanoparticles and (b) first and second cyclic Group IVA compounds in which the cyclic species predominantly contains Si and/or Ge atoms. The ink generally includes the composition and a solvent in which the composition is soluble. The method generally includes the steps of (1) printing the composition or ink on a substrate to form a pattern, and (2) curing the patterned composition or ink. In an alternative embodiment, the method includes the steps of (i) curing either a semiconductor nanoparticle composition or at least one cyclic Group IVA compound to form a thin film, (ii) coating the thin film with the other, and (iii) curing the coated thin film to form a semiconducting thin film.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: February 1, 2011
    Assignee: Kovio, Inc.
    Inventors: Klaus Kunze, Scott Haubrich, Fabio Zurcher, Brent Ridley, Joerg Rockenberger
  • Patent number: 7799302
    Abstract: A method of making hydrogenated Group IVA compounds having reduced metal-based impurities, compositions and inks including such Group IVA compounds, and methods for forming a semiconductor thin film. Thin semiconducting films prepared according to the present invention generally exhibit improved conductivity, film morphology and/or carrier mobility relative to an otherwise identical structure made by an identical process, but without the washing step. In addition, the properties of the present thin film are generally more predictable than those of films produced from similarly prepared (cyclo)silanes that have not been washed according to the present invention.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: September 21, 2010
    Assignee: Kovio, Inc.
    Inventors: Klaus Kunze, Wenzhuo Guo, Fabio Zurcher, Mao Takashima, Laila Francisco, Joerg Rockenberger, Brent Ridley
  • Patent number: 7767520
    Abstract: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: August 3, 2010
    Assignee: Kovio, Inc.
    Inventors: Arvind Kamath, James Montague Cleeves, Joerg Rockenberger, Patrick Smith, Fabio Zürcher
  • Patent number: 7767261
    Abstract: Compositions, inks and methods for forming a patterned silicon-containing film and patterned structures including such a film. The composition generally includes (a) passivated semiconductor nanoparticles and (b) first and second cyclic Group IVA compounds in which the cyclic species predominantly contains Si and/or Ge atoms. The ink generally includes the composition and a solvent in which the composition is soluble. The method generally includes the steps of (1) printing the composition or ink on a substrate to form a pattern, and (2) curing the patterned composition or ink. In an alternative embodiment, the method includes the steps of (i) curing either a semiconductor nanoparticle composition or at least one cyclic Group IVA compound to form a thin film, (ii) coating the thin film with the other, and (iii) curing the coated thin film to form a semiconducting thin film.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: August 3, 2010
    Assignee: Kovio, Inc.
    Inventors: Klaus Kunze, Scott Haubrich, Fabio Zurcher, Brent Ridley, Joerg Rockenberger
  • Patent number: 7750792
    Abstract: Multi-mode (e.g., EAS and RFID) tags and methods for making and using the same are disclosed. The tag generally includes an antenna, an electronic article surveillance (EAS) function block coupled to the antenna, and one or more identification function blocks coupled to the antenna in parallel with the EAS function block. The method of reading the tag generally includes the steps of applying an electric field to the tag, detecting the tag when the electric field has a relatively low power, and detecting an identification signal from the tag when the electric field has a relatively high power. The present invention advantageously enables a single tag to be used for both inventory and anti-theft purposes, thereby improving inventory management and control at reduced system and/or “per-article” costs.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: July 6, 2010
    Assignee: Kovio, Inc.
    Inventors: Patrick Smith, James Montague Cleeves, Vikram Pavate, Vivek Subramanian
  • Patent number: 7723457
    Abstract: Polysilanes, inks containing the same, and methods for their preparation are disclosed. The polysilane generally has the formula H-[(AHR)n(c-AmHpm-2)q]—H, where each instance of A is independently Si or Ge; R is H, -AaHa+1Ra, halogen, aryl or substituted aryl; (n+a)?10 if q=0, q?3 if n=0, and (n+q)?6 if both n and q?0; p is 1 or 2; and m is from 3 to 12. In one aspect, the method generally includes the steps of combining a silane compound of the formula AHaR14-a, the formula AkHgR1?h and/or the formula c-AmHpmR1fm with a catalyst of the formula R4xR5yMXz (or an immobilized derivative thereof) to form a poly(aryl)silane; then washing the poly(aryl)silane with an aqueous washing composition and contacting the poly(aryl)silane with an adsorbent to remove the metal M. In another aspect, the method includes the steps of halogenating a polyarylsilane to form a halopolysilane; and reducing the halopolysilane with a metal hydride to form the polysilane.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: May 25, 2010
    Assignee: Kovio, Inc.
    Inventors: Wenzhuo Guo, Vladimir K. Dioumaev, Joerg Rockenberger, Brent Ridley
  • Patent number: 7709307
    Abstract: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: May 4, 2010
    Assignee: Kovio, Inc.
    Inventors: Arvind Kamath, Patrick Smith, James Montague Cleeves
  • Patent number: 7701011
    Abstract: An electronic device, including a substrate, a plurality of first semiconductor islands on the substrate, a plurality of second semiconductor islands on the substrate, a first dielectric film on the first subset of the semiconductor islands, second dielectric film on the second semiconductor islands, and a metal layer in electrical contact with the first and second semiconductor islands. The first semiconductor islands and the first dielectric film contain a first diffusible dopant, and the second semiconductor islands and the second dielectric layer film contain a second diffusible dopant different from the first diffusible dopant. The present electronic device can be manufactured using printing technologies, thereby enabling high-throughput, low-cost manufacturing of electrical circuits on a wide variety of substrates.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: April 20, 2010
    Assignee: Kovio, Inc.
    Inventors: Arvind Kamath, James Montague Cleeves, Joerg Rockenberger, Patrick Smith, Fabio Zürcher
  • Patent number: 7691691
    Abstract: Thin film transistors (TFT) and methods for making same. The TFTs generally comprise: (a) a semiconductor layer comprising source and drain terminals and a channel region therebetween; (b) a gate electrode comprising a gate and a gate dielectric layer between the gate and the channel region; (c) a first dielectric layer adjacent to the gate electrode and in contact with the source and drain terminals, the first dielectric layer comprising a material which comprises a dopant therein; and (d) an electrically functional source/drain extensions in the channel region, adjacent to the source and drain terminals, comprising a material which comprises the same dopant as the first dielectric layer.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: April 6, 2010
    Assignee: Kovio, Inc.
    Inventor: James Montague Cleeves
  • Patent number: 7687327
    Abstract: Radio frequency identification (RFID) tags and processes for manufacturing the same. The RFID device generally includes (1) a metal antenna and/or inductor; (2) a dielectric layer thereon, to support and insulate integrated circuitry from the metal antenna and/or inductor; (3) a plurality of diodes and a plurality of transistors on the dielectric layer, the diodes having at least one layer in common with the transistors; and (4) a plurality of capacitors in electrical communication with the metal antenna and/or inductor and at least some of the diodes, the plurality of capacitors having at least one layer in common with the plurality of diodes and/or with contacts to the diodes and transistors. The method preferably integrates liquid silicon-containing ink deposition into a cost effective, integrated manufacturing process for the manufacture of RFID circuits. Furthermore, the present RFID tags generally provide higher performance (e.g.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: March 30, 2010
    Assignee: Kovio, Inc,
    Inventors: James Montague Cleeves, J. Devin MacKenzie, Arvind Kamath
  • Patent number: 7675464
    Abstract: A method of making a double-sided antenna for high frequency devices is discussed. The method includes forming metal patterns on both sides of a substrate having pre-formed connection holes. Preferably, the metal patterns are formed using a printing ink having a precursor and a solvent. In one embodiment, the metal patterns include coils which are formed on both sides of the substrate. In one embodiment, shunt bars are used to speed up the process of making the metal patterns. The shunt bars are punched out at the end of the process to electrically isolate the metal patterns.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: March 9, 2010
    Assignee: Kovio, Inc.
    Inventor: James Montague Cleeves
  • Patent number: 7674926
    Abstract: Dopant-group substituted (cyclo)silane compounds, liquid-phase compositions containing such compounds, and methods for making the same. Such compounds (and/or ink compositions containing the same) are useful for printing or spin coating a doped silane film onto a substrate that can easily be converted into a doped amorphous or polycrystalline silicon film suitable for electronic devices. Thus, the present invention advantageously provides commercial qualities and quantities of doped semiconductor films from a doped “liquid silicon” composition.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: March 9, 2010
    Assignee: Kovio, Inc.
    Inventors: Wenzhuo Guo, Vladimir K. Dioumaev, Brent Ridley, Fabio Zūrcher, Joerg Rockenberger, James Montague Cleeves
  • Patent number: 7619248
    Abstract: A MOS transistor with self-aligned source/drain terminals, and methods for its manufacture. The transistor generally includes an electrically functional substrate, a dielectric film on portions of the substrate, a gate on the dielectric film, and polycrystalline source and drain terminals self-aligned with the gate. The method generally includes forming an amorphous semiconductor material on a gate and on exposed portions of an electrically functional substrate, irradiating an upper surface of the amorphous semiconductor material to form self-aligned polycrystalline semiconducting source/drain terminal layers, and (optionally) selectively removing the non-irradiated amorphous semiconductor material portions. The present invention advantageously provides MOS thin film transistors having reliable electrical characteristics quickly, efficiently, and/or at a low cost by eliminating one or more conventional photolithographic steps.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: November 17, 2009
    Assignee: Kovio, Inc.
    Inventor: James Montague Cleeves
  • Patent number: 7553545
    Abstract: Compositions, inks and methods for forming a patterned silicon-containing film and patterned structures including such a film. The composition generally includes (a) passivated semiconductor nanoparticles and (b) first and second cyclic Group IVA compounds in which the cyclic species predominantly contains Si and/or Ge atoms. The ink generally includes the composition and a solvent in which the composition is soluble. The method generally includes the steps of (1) printing the composition or ink on a substrate to form a pattern, and (2) curing the patterned composition or ink. In an alternative embodiment, the method includes the steps of (i) curing either a semiconductor nanoparticle composition or at least one cyclic Group IVA compound to form a thin film, (ii) coating the thin film with the other, and (iii) curing the coated thin film to form a semiconducting thin film.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: June 30, 2009
    Assignee: Kovio, Inc.
    Inventors: Klaus Kunze, Scott Haubrich, Fabio Zurcher, Brent Ridley, Joerg Rockenberger
  • Patent number: 7528017
    Abstract: Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (Vt) of a diode manufactured using printing or laser writing techniques. The present invention advantageously utilizes the separation between the Vt of an NMOS TFT (Vtn) and the Vt of a PMOS TFT (Vtp) to establish and/or improve stability of a forward voltage drop across a printed or laser-written diode. Further applications of the present invention relate to reference voltage generators, voltage clamp circuits, methods of controlling voltages on related or differential signal transmission lines, and RFID and EAS tags and sensors.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: May 5, 2009
    Assignee: Kovio, Inc.
    Inventors: Vivek Subramanian, Patrick Smith