Abstract: The present invention is directed to data communication systems and techniques thereof. In a specific embodiment, the present invention provides a network connector that includes an interface for connecting to a host. The interface includes a circuit for utilizing two data paths for the host. The circuit is configured to transform the host address to different addresses based on the data path being used. There are other embodiments as well.

Abstract: A first communication device generates a beacon frame that includes i) parameters of a broadcast target wake time (TWT) schedule and ii) information regarding a quantity of client stations that have currently joined the broadcast TWT schedule. The first communication device transmits the beacon frame to inform one or more second communication devices of i) the parameters of the broadcast TWT schedule and ii) the quantity of client stations that have currently joined the broadcast TWT schedule.

Abstract: An Ethernet transceiver is disclosed. The Ethernet transceiver includes transceiver circuitry to couple to one end of an Ethernet link. The transceiver circuitry includes transmit circuitry to transmit high-speed Ethernet data along the Ethernet link at a first data rate and receiver circuitry. The receiver circuitry includes adaptive filter circuitry and correlator circuitry. The receiver circuitry is responsive to an inline signal to operate in a low-power alert mode with the adaptive filter circuitry disabled and to receive alert signals from the Ethernet link simultaneous with transmission of the Ethernet data by the transmit circuitry. The alert signals are detected by the correlator circuitry and include a sequence of alert intervals exhibiting encoded data at a second data rate less than the first data rate.

Abstract: An interface in a communications system includes a physical layer transceiver (PHY) for coupling to a wireline channel medium, and for coupling to a functional device via a single-ended cable. The PHY is an integrated circuit (IC) device having first and second differential input/output (I/O) conductors for coupling to the functional device, an impedance element configured to terminate a first one of the differential I/O conductors to a system ground, a second one of the differential I/O conductors being coupled to the single-ended cable, and a common-mode filter coupled to both of the differential I/O conductors. The PHY may further include a printed circuit board (PCB), with the IC device being mounted on the PCB, the first and second differential I/O conductors being signal traces on the PCB. The single-ended cable may be a coaxial cable.

Abstract: A method of operating an Ethernet transceiver includes initializing the Ethernet transceiver during a training mode of operation by monitoring background link operating characteristics with on-chip circuitry during a non-data-transfer interval to establish a baseline alien crosstalk value. Training data is then transmitted at a first transmit power level and first data rate to a link partner during a data transfer interval. The link is monitored with the on-chip circuitry during the data transfer interval to detect feedback indicating alien crosstalk effects to neighboring Ethernet links due to the transmitting. The first data rate and/or first transmit power level is then adjusted to an adjusted second data rate and/or second transmit power level based on the feedback. The Ethernet transceiver is then operated in a normal data transfer mode utilizing the adjusted second data rate and/or transmit power level.

Abstract: Systems and methods of selecting a collection of compatible issue-ready instructions for parallel execution by functional units in a superscalar processor in a single clock cycle. All possible instructions (opcodes) to be executed by the functional units are pre-arranged into several scenarios based on potential resource conflicts among the instructions. Each scenario includes multiple groups of predefined instructions. During operation, concurrently for all the groups, an issue-ready instruction is identified with reference to each group based on group-specific selection policies. Further, based on the identified instructions, predefined policies are applied to select one or more scenarios and select among the picks of the selected scenarios. As a result, the output instructions of the selected scenarios are issued for parallel execution by the functional units.

Abstract: A communication device is configured to receive data at a first data rate and to transmit the data at a second data rate that is greater than the first data rate. The communication device includes a plurality of communication pipelines and a multiplexer. Each communication pipeline is configured to receive a respective input data stream including first data blocks having a first format compatible for transmission at the first data rate, convert the first data blocks into second data blocks having a second format compatible for transmission at the second data rate, and provide an indication when one of the input data streams that is expected to be received is not received. The multiplexer is configured to receive the second data blocks from the communication pipelines and to generate an output data stream for transmission at the second data rate when one of the input data streams is not received.

Abstract: Transceiver circuitry in an integrated circuit device includes a receive path including an analog front end for receiving analog signals from an analog transmission path and conditioning the analog signals, and an analog-to-digital converter configured to convert the conditioned analog signals into received digital signals for delivery to functional circuitry, and a transmit path including a digital front end configured to accept digital signals from the functional circuitry and to condition the accepted digital signals, and a digital-to-analog converter configured to convert the conditioned digital signals into analog signals for transmission onto the analog transmission path. At least one of the analog front end and the digital front end introduces distortion and outputs a distorted conditioned signal.

Abstract: In an embodiment, a method includes programming a control signal that specifies a target resistance and a target voltage in a circuit. The method further includes sending the control signal to at least one transistor configured to control a current flow in the circuit. The method further includes providing, as an output, a signal with the target voltage and target resistance.

Abstract: A coherent optical receiver includes equalizer circuitry having a plurality of taps, the equalizer circuitry being configured to receive an input signal and compensate for polarization mode dispersion affecting the input signal to generate a compensated input signal. The coherent optical receiver further includes error evaluation circuitry configured to calculate a determinant of a frequency-domain (FD) coefficient-based matrix using a plurality of tap signals from among the plurality of taps, adjust an error of convergence of the compensated input signal to generate an adjusted input signal, and iteratively adjust the determinant of the FD coefficient-based matrix based on the adjusted input signal to minimize the error of convergence.

Abstract: A method for writing data to a magnetic data storage medium includes detecting whether the duration, before occurrence of a data transition, of data to be written exceeds a predetermined threshold, and, when the duration, before the occurrence of the data transition, of the data to be written exceeds the predetermined threshold, writing the data by applying an initial pulse and then maintaining a steady-state write current for a defined interval, and when the duration, before the occurrence of the data transition, of the data to be written is at most equal to the predetermined threshold, writing the data by applying the initial pulse without applying a steady-state write current before the data transition. The predetermined threshold may be determined by size of a magnetic bubble formed when writing a single bit to the magnetic data storage medium. A subsequent pulse may be applied following the defined interval.

Abstract: A packet to be forwarded over a computer network to a destination is received. A group of multiple network paths is available to forward to the packet to the destination. One or more path selection factors are determined to be used to identify a specific network load balancing algorithm to select a specific network path from the group of multiple network paths. The one or more path selection factors include at least one path selection factor determined based at least in part on a dynamic state of the computer network or a network node in the computer network. In response to selecting, by the specific network load balancing algorithm, the specific network path from among the group of multiple network paths, the packet is forwarded over the specific network path.

Abstract: An optical transmitter includes a first encoder, a first interleaver, a second encoder, a mapper, a second interleaver, and a frame generator. The first encoder is configured to encode data using a staircase code to generate first codewords. The first interleaver is configured to interleave the first codewords using convolutional interleaving to spread a transmission order of the first codewords. The second encoder is configured to encode the interleaved first codewords using a second code to generate second codewords. The mapper is configured to map the second codewords to transmit symbols. The second interleaver is configured to interleave the transmit symbols to distribute the transmit symbols between pilot symbols. The frame generator is configured to generate a transmit frame including the interleaved transmit symbols and the pilot symbols.

Abstract: A first communication device determines that a trigger frame and another frame are to be transmitted to at least a second communication device. The first communication device determines whether the second communication device announced support of aggregation of buffer status report (BSRP) trigger frames with additional frames. In response to the first communication device determining that the second communication device announced support of aggregation of BSRP trigger frames with additional frames, the first communication device generates an aggregate media access control protocol data unit (A-MPDU) to include the BSRP trigger frame and the other frame, and transmits the A-MPDU within a packet. In response to the first communication device determining that the second communication device did not announce support of aggregation of BSRP trigger frames with additional frames, the first communication device transmits a packet having only the BSRP trigger frame.

Abstract: Described herein are systems and methods for secure multithread execution. For example, some methods include fetching an instruction of a first thread from a memory into a processor pipeline that is configured to execute instructions from two or more threads in parallel using execution units of the processor pipeline; detecting that the instruction has been designated as a sensitive instruction; responsive to detection of the sensitive instruction, disabling execution of instructions of threads other than the first thread in the processor pipeline during execution of the sensitive instruction by an execution unit of the processor pipeline; executing the sensitive instruction using an execution unit of the processor pipeline; and, responsive to completion of execution of the sensitive instruction, enabling execution of instructions of threads other than the first thread in the processor pipeline.

Abstract: A laser chip for flip-chip bonding on a silicon photonics chip with passive alignment features. The laser chip includes a chip body made of a p-region and a n-region in vertical direction and extended from a front facet to a rear facet in longitudinal direction, a pair of first vertical stoppers formed respectively beyond two sides of the chip body based on a wider width of the n-region, an active region buried in the chip body between the p-region and the n-region in the vertical direction and extended from the front facet to the rear facet in the longitudinal direction, an alignment mark formed on a top surface of the p-region near the front facet with a lateral distance defined in sub-micron precision relative to the active region; and a thin metal film on the surface of the p-region having a cleaved edge shared with the front facet.

Abstract: A master integrated circuit (IC) chip includes transmit circuitry and receiver circuitry. The transmit circuitry includes a timing signal generation circuit to generate a first timing signal, and a driver to transmit first data in response to the first timing signal. A timing signal path routes the first timing signal in a source synchronous manner with the first data. The receiver circuitry includes a receiver to receive second data from a slave IC chip, and sampling circuitry to sample the second data in response to a second timing signal that is derived from the first timing signal.

Abstract: Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels.

Abstract: Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor. In an exemplary embodiment, a method includes receiving a plurality of discrete Fourier transform (DFT) jobs. Each job identifies a computation of a DFT of a particular point size. The method also includes bundling selected jobs having a selected point size into a mega-job, and identifying a radix factorization for the selected point size. The radix factorization includes one or more stages and each stage identifies a radix computation to be performed. The method also includes computing, for each stage, the identified radix computations for the selected jobs in the mega-job. The radix computations for each stage are performed for the selected jobs before performing radix computations for a subsequent stage. The method also includes outputting DFT results for the selected jobs in the mega-job.

Abstract: Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor. In an exemplary embodiment, a method includes receiving a plurality of discrete Fourier transform (DFT) jobs. Each job identifies a computation of a DFT of a particular point size. The method also includes bundling selected jobs having a selected point size into a mega-job, and identifying a radix factorization for the selected point size. The radix factorization includes one or more stages and each stage identifies a radix computation to be performed. The method also includes computing, for each stage, the identified radix computations for the selected jobs in the mega-job. The radix computations for each stage are performed for the selected jobs before performing radix computations for a subsequent stage. The method also includes outputting DFT results for the selected jobs in the mega-job.