Abstract: A lateral double-diffused metal oxide semiconductor (LDMOS) device is disclosed. The LDMOS device comprises a gate region and a body region under the gate region. The LDMOS device includes an enhanced drift region under the gate region. The enhanced drift region touches the body region. By designing the device such that the enhanced drift region overlaps and compensates the lateral tail of the body region of the LDMOS transistor, the Ron*area product is reduced. Accordingly, the on-resistance is significantly reduced while minimally affecting the breakdown voltage of the device.

Abstract: A semiconductor relay switch having two data ports receiving incoming signals and a power supply terminal receiving a power supply voltage is responsive to a power supply voltage level and an energy level of the incoming signals to open and close its conduction paths. The relay switch is open when a valid power supply level is detected and when there is no supply power on the power supply terminal but a high energy level is detected in the incoming signals. The relay switch is closed to allow conduction between the two data ports only when there is no power supply voltage on the power supply terminal and an energy level below a predetermined threshold is detected in the incoming signals. In one embodiment, the semiconductor relay switch includes a main conduction switch circuit, an energy detect circuit and a control signal generator.

Abstract: A method for providing a high power, low resistance, high efficient vertical DMOS device is disclosed. The method comprises providing a semiconductor substrate with a source body structure thereon. The method further comprises providing a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing.

Abstract: A power controller system is described herein, which may consist of one or more power controller ICs and other components. Each power controller selectively couples power supply voltages to a plurality of electrical devices, such as cards that have been inserted into expansion slots in a server. To simplify processing by a system processor monitoring the health of the power subsystem, each power controller IC asserts a power-good signal at a power-good terminal only if the operating conditions for all channels are satisfactory. A power good signal is generated even if a channel is not supplying power to a channel due to a card retention switch signal not being asserted or the channel is not enabled. The power-good signals from all power controllers in the system are then ANDed together to determine if any of the power controllers are experiencing unsatisfactory conditions.

Abstract: A power switch circuit and method is provided for having the capability of (1) a power switch circuit having a POR in which the switch is enabled at a predetermined voltage such that the switch is unable to be activated when a minimum lower input voltage is not achieved, to avoid potential conflicts in synchronization and resets with other integrated circuits or chips of an affected system; (2) a POR designed with a delay circuit providing for coordinated stabilization of the power switch before each ON-OFF transition period,; (3) using a controlled peaking current in the POR circuit to provide precise RC delay to avoid instability during transition; and (4) a POR providing an externally controlled voltage to power-up other components in the system when energizing of the first component occurs satisfactorily.

Abstract: A MOS transistor includes a conductive gate insulated from a semiconductor layer by a first dielectric layer, lightly-doped source/drain regions being formed self-aligned to respective first and second edges of the conductive gate, a source region being formed self-aligned to a first spacer, a drain region being formed a first distance away from the edge of a second spacer, a source contact opening and source metallization formed above the source region, and a drain contact opening and drain metallization formed above the drain region. The lightly-doped source region remains under the first spacer while the lightly-doped drain region remains under the second spacer and extends over the first distance to the drain region. The distance between the first edge of the conductive gate to the source contact opening is the same as the distance between the second edge of the conductive gate to the drain contact opening.

Abstract: A method for providing adaptive compensation for an electrical circuit where the electrical circuit includes an inductor-capacitor network connected in a feedback loop being compensated by a first compensation capacitance value and a second compensation capacitance value defining the frequency locations of two compensation zeros includes: measuring the inductance value of the inductor; when the inductance value is greater than a first threshold value, increasing the first and second compensation capacitance values so that the frequency locations of the two compensation zeros are adjusted for compensating the poles introduced by the first inductor and the first capacitor; and when the inductance value is less than the first threshold value, decreasing the first and second compensation capacitance values so that the frequency locations of the two compensation zeros are adjusted for compensating the poles introduced by the first inductor and the first capacitor.

Abstract: An LED driver is disclosed that boosts an input voltage to drive any number of LEDs in series. The driver includes a switch-mode current regulator that supplies regulated current pulses to the LEDs. No high voltage output capacitor is used to smooth the current pulses, so the LEDs are turned on any off at the switching frequency. Also, no blocking diode between the switching transistor and the LEDs is used. The cathode of the “bottom” LED in the string is connected to ground via a current sense resistor. In parallel with the sense resistor is connected an RC filter using a small, low voltage filter capacitor. The RC filter provides a substantially smooth feedback voltage for the current regulator to control the duty cycle of the switching transistor so that the feedback voltage matches a reference voltage.

Abstract: An improved diode is disclosed. The diode comprises a Schottky diode and a LDMOS device coupled in series with the Schottky diode. In a preferred embodiment, a forward current from the Schottky diode is allowed to flow through the channel of a depletion mode LDMOS that allows gate control over Schottky forward current. Integrating the Schottky diode into the drain of the depletion mode LDMOS forms the device structure.

Abstract: An LED driver is disclosed that drives LEDs connected in parallel. Instead of applying current to all the parallel-connected LEDs at the same time, under control of a common PWM brightness control signal, the application of current to each parallel path is staggered by using staggered brightness control signals. The turning on of the LEDs in the different parallel paths will have the same duty cycle but will be out of phase. This reduces ripple in the power supply by reducing the magnitude of the instantaneous current sink. In one embodiment, a shift register contains a binary representation of the PWM duty cycle, and a clock shifts the bits along the shift register. The PWM brightness control signals for each parallel path of LEDs are tapped from different positions along the shift register so that the PWM brightness control signals are identical but staggered.

Abstract: A method in an Ethernet physical transceiver device for selecting a transmission speed includes resetting a first register and a count value, establishing a link with a remote network device at a first transmission speed, incrementing the first register to a first value, monitoring the link by counting the number of detected false carrier events in the incoming transmission as the count value, and at the expiration of a first time period, comparing the count value of false carrier events to a predetermined threshold. The method continues with reducing the first transmission speed when the count value exceeds the predetermined threshold, maintaining the first transmission speed when the count value is less than the predetermined threshold, and when the first register has a first value, incrementing the first register to a second value and repeating the steps of monitoring the link to reducing the first transmission speed.

Abstract: A driver for driving a plurality of light emitting diodes (LEDs) is formed of a plurality of LED controllers connected in series between a power supply and a reference voltage. Each controller drives one or more LEDs directly connected to it. Each controller has a voltage input terminal coupled to an output terminal of an adjacent upstream controller, and an output terminal coupled to the voltage input terminal of an adjacent downstream controller. Each controller has a normally-on bypass switch coupled between its voltage input terminal and the voltage input terminal of the adjacent upstream controller. The bypass switch completely bypasses the adjacent upstream controller when the adjacent downstream controller detects that its input voltage is below a threshold insufficient to drive the LED in the adjacent upstream controller. The bypass switch is turned off if the voltage is above the threshold.

Abstract: A power controller system is described herein, where a power-good signal (PWRGD) is asserted followed by a slightly delayed power-good signal (DLY_PWRGD) upon the system powering up. This PWRGD signal indicates that good power is being supplied to the card or other equipment, and the delayed signal tells a system processor that it is now ok to communicate with the card or other equipment. This delay allows the card or other equipment to reach a steady state condition before being declared operational by the power controller. When powering down the equipment, the DLY_PWRGD signal is first deasserted and power is decoupled from the card or other equipment. The PWRGD signal is then deasserted after a short delay. This short delay allows circuitry within the card to be properly shut down by, for example, carrying out a shutdown routine, using stored charge in the card to temporarily power the card. A state machine is used to carry out the four-state power up and power down sequence.

Abstract: In one embodiment, relatively thin but wide metal bus strips overlying a high power FET are formed to conduct current to the source and drain narrow metal strips. A passivation layer is formed over the surface of the FET, and the passivation layer is etched to expose almost the entire top surface of the bus strips. A copper seed layer is then formed over the surface of the wafer, and a mask is formed to expose only the seed layer over the bus strips. The seed layer over the bus strips is then copper or gold electroplated to deposit a very thick metal layer, which effectively merges with the underlaying metal layer, to reduce on-resistance. The plating metal does not need to be passivated due to its thickness and wide line/space. Other techniques may also be used for depositing a thick metal over the exposed bus strips.

Abstract: An optimized output voltage circuit and technique obtainable without trimming is set forth. A voltage reference circuit and method devoid of trim resistors comprising a high gain amplifier, a plurality of bandgap resistors, and at least a plurality of bipolar devices interconnected across circuitry in a predetermined configuration having emitter areas greater than traditional emitter areas of traditional bipolar devices is set forth.

Abstract: The present invention relates generally to semiconductor wafer fabrication and more particularly but not exclusively to predictive, pre-fabrication methodologies for determining inefficiencies in an integrated circuit (IC) design. The present invention, in one or more implementations, provides an effective pre-production methodology for predicting the efficiency and behavior of a designed ESD protective circuit and testing the ESD protective circuit with a simulated IC. The method of the present invention yields predictive results that have been comparatively tested.

Abstract: A method for providing a high power, low resistance, high efficient vertical DMOS device is disclosed. The method comprises providing a semiconductor substrate with a source body structure thereon. The method further comprises providing a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing.

Abstract: An NMOS transistor includes a semiconductor substrate of a first conductivity type, first and second well regions of a second conductivity type formed spaced apart in the substrate, a conductive gate formed over the region between the spaced apart first and second well regions where the region of the substrate between the spaced apart first and second well regions forms the channel region, dielectric spacers formed on the sidewalls of the conductive gate, first and second heavily doped source and drain regions of the second conductivity type formed in the semiconductor substrate and being self-aligned to the edges of the dielectric spacers. The first and second well regions extend from the respective heavily doped regions through an area under the spacers to the third well region. The first and second well regions bridge the source and drain regions to the channel region of the transistor formed by the third well.

Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a floor for a semiconductor device by utilizing a CMOS process. The method further includes providing a BiCMOS-like process on top of the floor to further fabricate the semiconductor device, wherein the BiCMOS-like process and the CMOS process provides the semiconductor device.

Abstract: A single chip hybrid regulator is disclosed having a first stage being a switching regulator and a second stage being a linear regulator. The switching regulator uses a filter circuit including an inductor and a capacitor. To make the hybrid regulator very small, the inductor value is selected so that the inductor saturates at a current level well below the maximum load current for the regulator. At low load currents, the small inductor does not saturate, and the regulated voltage applied to the input of the linear regulator presents only a small differential voltage across the series transistor of the linear regulator, resulting in very little power being wasted by the series transistor. At higher currents, the small inductor begins to saturate or fully saturates; however, the increased ripple is smoothed by the linear regulator.