Abstract: A DC-to-DC, buck-boost voltage converter includes a duty cycle controller configured to generate control signals for a buck driver configured to drive first and second buck switching transistors at a buck duty cycle and to generate control signals for a boost driver configured to drive first and second boost switching transistors at a boost duty cycle. The duty cycle controller includes at least a duty cycle timer and an offset timer where the duty cycle controller applies the duty cycle timer and the offset timer to control transitions between the buck, the buck-boost and the boost operation modes of the voltage converter.

Abstract: In an average-current mode control type buck-boost PWM converter, a sample and hold circuit is inserted in the current loop to avoid problems associated with ripple of the average inductor current demand signal. The rippling average inductor current is generated by a differential transconductance amplifier having applied to its inputs an error signal and a signal corresponding to the instantaneous current through the inductor, where the output of the amplifier is filtered. The rippling average inductor current is sampled and held at the beginning of each switching cycle, prior to the average inductor current demand signal being compared to buck and boost sawtooth waveforms. By using the sample and hold circuit, the feedback loops are easier to stabilize, and the converter cannot switch modes during a switching cycle.

Abstract: In one embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and a secondary signal path including a pulse shaping stage incorporating a network and a scaling stage. The pre-emphasis circuit generates an overshoot pulse with variable pulse width. In another embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and one or more secondary signal paths incorporating a network implementing a specific transient response. Each of the secondary signal paths includes a scaling stage and a shaping stage each with programmable bias current. The scaling stage can be configured before or after the shaping amplifier. The pre-emphasis circuit generates an overshoot signal with variable amplitude and/or variable width.

Abstract: In one embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and a secondary signal path including a pulse shaping stage incorporating a network and a scaling stage. The pre-emphasis circuit generates an overshoot pulse with variable pulse width. In another embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and one or more secondary signal paths incorporating a network implementing a specific transient response. Each of the secondary signal paths includes a scaling stage and a shaping stage each with programmable bias current. The scaling stage can be configured before or after the shaping amplifier. The pre-emphasis circuit generates an overshoot signal with variable amplitude and/or variable width.

Abstract: A transmission line pre-emphasis circuit includes a primary signal path receiving a digital data stream and generating a primary output current indicative of the digital data stream, one or more secondary signal paths each incorporating a network implementing a specific transient response where the one or more secondary signal paths receive the digital data stream and generate secondary output currents representing one or more overshoot signals indicative of the transient response of the respective network. The one or more secondary signal paths have variable gain being programmed through respective DC programming signals. The secondary output currents are summed with the primary output current. The transmission line pre-emphasis circuit further includes an output loading stage coupled to generate from the summed current a pre-emphasized digital output signal indicative of the one or more overshoot signals added to the digital data stream.

Abstract: A transmission line equalizer includes multiple signal paths connected in parallel between an equalizer input signal and an output amplifier where each signal path has a network implementing a specific frequency dependent response and each signal path implements current gain amplification with one or more of the signal paths having a variable gain programmed through a time invariant, DC programming signal. Furthermore, one or more of the signal paths implements linear-to-nonlinear signal transformations and compensating nonlinear-to-linear signal transformations to generate linearized output signals at the one or more signal paths. The equalizer further includes the output amplifier summing output signals from the multiple signal paths to generate an equalized output signal. In operation, the gain of the one or more signal paths is varied to establish the relative proportions of the output signals generated by each signal path and summed at the output amplifier.

Abstract: A circuit breaker for a power controller integrated circuit is described where an analog timer and a digital timer are provided in parallel. The digital timer provides a fixed, on-chip maximum delay during an overcurrent condition to ensure the transistor will not be damaged. The analog timer allows the user to select an external capacitor or resistor to provide a delay time that is shorter than the time provided by the digital timer. Accordingly, the power controller retains all the flexibility of an analog timer but prevents the overcurrent exceeding a maximum time limit. An autoretry circuit is also included in the power controller which prevents the duty cycle from exceeding a maximum. The autoretry timer is a digital timer that uses the same oscillator as the digital timer for the circuit breaker so the ratio of the delay times is known and fixed.

Abstract: A MOS transistor includes a body region of a first conductivity type, a conductive gate and a first dielectric layer, a source region of a second conductivity type formed in the body region, a heavily doped source contact diffusion region formed in the source region, a lightly doped drain region of the second conductivity type formed in the body region where the lightly doped drain region is a drift region of the MOS transistor, a heavily doped drain contact diffusion region of the second conductivity type formed in the lightly doped drain region; and an insulating trench formed in the lightly doped drain region adjacent the drain contact diffusion region. The insulating trench blocks a surface current path in the drift region thereby forming vertical current paths in the drift region around the bottom surface of the trench.

Abstract: A power switch circuit and method is provided for having the capability of (1) a power switch circuit having a POR in which the switch is enabled at a predetermined voltage such that the switch is unable to be activated when a minimum lower input voltage is not achieved, to avoid potential conflicts in synchronization and resets with other integrated circuits or chips of an affected system; (2) a POR designed with a delay circuit providing for coordinated stabilization of the power switch before each ON-OFF transition period; (3) using a controlled peaking current in the POR circuit to provide precise RC delay to avoid instability during transition; and (4) a POR providing an externally controlled voltage to power-up other components in the system when energizing of the first component occurs satisfactorily.

Abstract: The present invention relates generally to semiconductor wafer fabrication and more particularly but not exclusively to predictive, pre-fabrication methodologies for determining inefficiencies in an integrated circuit (IC) design. The present invention, in one or more implementations, provides an effective pre-production methodology for predicting the efficiency and behavior of a designed ESD protective circuit and testing the ESD protective circuit with a simulated IC. The method of the present invention yields predictive results that have been comparatively tested.

Abstract: The present invention is one or more implementations is a method of fabricating a semiconductor for improved oxide thickness control, defining a process tool, determining and evaluating performance variables, determining a performance impact factor and thereafter modifying control of the process tool in the fabrication process to operate in direct relation to the determined results of the present invention. The present invention sets forth definitive advantages in reducing engineering time, improving process controls and improving cycle-times.

Abstract: A method is described for converting an existing die, originally designed for a non-chip-scale package, to a chip-scale package die, where the die's bonding pads are located in positions within a defined grid of candidate positions. In the first step, the die's layout, comprising its outer boundaries and areas needed to be electrically connected to bonding pads, are shifted relative to a grid of candidate positions for the bonding pads until an optimal alignment is identified. Bonding pads positions on the die are then selected corresponding to optimum grid positions within the outer boundaries of the die. The die is then fabricated using the original masks to form at least the semiconductor regions and using a new set of masks for defining the new locations of the bonding pads for the chip-scale package. The chip-scale package is then bonded to a PCB using chip-scale package technology.

Abstract: A method in an Ethernet controller for allocating memory space in a buffer memory between a transmit queue (TXQ) and a receive queue (RXQ) includes allocating initial memory space in the buffer memory to the RXQ and the TXQ; defining a RXQ high watermark and a RXQ low watermark; receiving an ingress data frame; determining if a memory usage in the RXQ exceeds the RXQ high watermark; if the RXQ high watermark is not exceeded, storing the ingress data frame in the RXQ; if the RXQ high watermark is exceeded, determining if there are unused memory space in the TXQ; if there are no unused memory space in the TXQ, transmitting a pause frame to halt further ingress data frame; if there are unused memory space in the TXQ, allocating unused memory space in the TXQ to the RXQ; and storing the ingress data frame in the RXQ.

Abstract: A method for forming identical isotropic etch patterns in an etch system is disclosed. The method comprises providing a wafer paddle, a wafer, a plurality of identical etch systems, utilizing identical etch recipes within each of the plurality of etch systems, providing a fixed temperature stability time FTST for each system so that the heat transfer from the paddle to the wafer is constant, wherein the FTST is the same on each of the plurality of etch systems; and utilizing the plurality of identical etch systems to produce identical etches on each of the wafers based upon the FTST, wherein a five-second preheat step in the etch process is not utilized.

Abstract: A Schottky or PN diode is formed where a first cathode portion is an N epitaxial layer that is relatively lightly doped. An N+ buried layer is formed beneath the cathode for conducting the cathode current to a cathode contact. A more highly doped N-well is formed, as a second cathode portion, in the epitaxial layer so that the complete cathode comprises the N-well surrounded by the more lightly doped first cathode portion. An anode covers the upper areas of the first and second cathode portions so both portions conduct current when the diode is forward biased. When the diode is reverse biased, the depletion region in the central N-well will be relatively shallow but substantially planar so will have a relatively high breakdown voltage. The weak link for breakdown voltage will be the curved edge of the deeper depletion region in the lightly doped first cathode portion under the outer edges of the anode. Therefore, the N-well lowers the on-resistance without lowering the breakdown voltage.

Abstract: A single chip receiver is disclosed herein. The chip only requires an external antenna for operation. A decoder is formed on chip for performing logical operations on demodulated digital data. A baseband filter is controlled by external control signals to have one of a plurality of discrete frequency response bandwidths depending on the type of signal to be received. To compensate for process variations in the implementation of the IC, bias currents setting the operating conditions for various amplifiers and other components in the system are adjusted based on frequency control signals in a PLL circuit in the local oscillator. Since the magnitude of the control signal reflects the process variations, the bias currents are adjusted based on the control signal to offset these variations in other portions of the receiver.

Abstract: An accelerator circuit is incorporated in a laser diode system for accelerating the turn-on operation of the laser diode independent of the control loop bandwidth of the laser diode system. The accelerator circuit provides a boost current to a compensation capacitor upon laser turn-on which compensation capacitor operates to establish the control loop bandwidth of the laser diode system. The boost current enables the control loop to increase the bias current to the laser diode quickly. When the laser diode reaches the desired operating point, the boost current is terminated and the control loop of the laser diode system resumes normal control of the bias current. In one embodiment, the accelerator circuit includes a timer circuit controlling a current source to implement open loop turn-on control. In another embodiment, the accelerator circuit includes a comparator circuit working in conjunction with an one-shot logic circuit for providing close loop control.

Abstract: An integrated circuit capable of dual configuration of data flow and operable in a plurality of operational modes is provided. The circuit includes eight corner pins, wherein the eight corner pins comprise a first corner pin and a second corner pin on each side of the circuit in each of four side sets, wherein a first corner pin of one side of the circuit is proximate and adjacent to a second corner pin of an adjacent side counterclockwise from the first corner pin and together constitute a paired corner set, each paired corner set comprising a differential input and a differential output.

Abstract: A receiver converts an analog signal, derived from light pulses in a GPON fiber optic system, to clean digital electrical signals. A photodetector and transimpedance amplifier (TIA) convert the light pulses to analog electrical signals. A reset signal generated by a media access controller (MAC) in the GPON system signifies the start of a new burst of data. The receiver has a switchable low pass filter that establishes the threshold voltage for determining whether the analog signal is a logical 1 or a logical 0. At the very start of a new burst, the low pass filter has a fast time constant to quickly establish the threshold voltage for the burst. At a later time during the burst, the low pass filter is switched to have a slow time constant to create a relatively stable threshold voltage.

Abstract: A circuit is described for automatically adjusting a phase of an input register load clock to be synchronized with transitions of data bits forming an n-bit word. The circuit detects the first transition of a data bit in the n-bit word. The circuit then time-shifts the input clock, to generate a shifted clock, so that a triggering edge of the shifted clock occurs sometime after generation of the transition detect signal, such as in the middle third of a data cycle. Shifting the input clock may be performed by multiplying the input clock to generate a plurality of sub-clock cycles and selecting one of the sub-clock cycles as the start of the shifted clock cycle. The parallel data are applied to inputs of input registers clocked using the shifted clock as the load clock. Thus, the load clock occurs at an optimum time near the middle of a data cycle.