Abstract: A single field photomask includes a first set of targets formed on a first side of the photomask, and a second set of targets formed on a second side of the photomask, opposite the first side. In operation, the photomask is to be applied to a wafer without any alignment marks. The photomask forms a first set of alignment marks in the wafer from the first set of targets, and the photomask further forms a second set of alignment marks in the wafer from the second set of targets. The first set of alignment marks is used to align to a first field mask and the second set of alignment marks is used to align to a second field mask to stitch an image of the first field mask to an image of the second field mask.

Abstract: In a buck-boost converter, the method compensates for the boost mode power switch having a minimum on-time when entering the buck-boost mode from the buck mode by immediately decreasing a duty cycle of the buck mode power switch upon entering the buck-boost mode. This prevents the inductor current from being higher at the end of the switching cycle than at the beginning of the cycle, so the output voltage stays regulated without the converter oscillating between the buck mode and the buck-boost mode. The duty cycle of the buck power switch is increased in the buck-boost mode as the input voltage further falls and the boost power switch duty cycle is increased. Upon transitioning into the boost mode, the duty cycle of the boost power switch is immediately reduced to compensate for the buck switching being stopped and the buck power switch having a minimum off-time.

Abstract: A method to form a LDMOS transistor includes forming a gate/source/body opening and a drain opening in a field oxide on a substrate structure, forming a gate oxide in the gate/source/body opening, and forming a polysilicon layer over the substrate structure. The polysilicon layer is anisotropically etched to form polysilicon spacer gates separated by a space in the gate/source/body opening and a polysilicon drain contact in the drain opening. A body region is formed self-aligned about outer edges of the polysilicon spacer gates, a source region is formed self-aligned about inner edges of the polysilicon spacer gates, and a drain region is formed under the polysilicon drain contact and self-aligned with respect to the polysilicon spacer gates. A drift region forms in the substrate structure between the body region and the drain region, and a channel region forms in the body region between the source region and the drift region.

Abstract: A driver circuit for controlling a high-side power switch of a switching regulator includes: a logic circuit configured to generate a gate control signal for turning on the power switch; a diode having coupled to a first power supply voltage; a capacitor having a first electrode coupled to the cathode of the diode and a second electrode coupled to the switching output voltage; and a delay circuit configured to receive the gate control signal and to generate a delayed gate control signal. In operation, the capacitor is precharged to about the first power supply voltage. When the power switch is turned on, a first output drive transistor is turned on to distribute the charge stored on the capacitor to the gate terminal of the high-side power switch, and after the predetermined delay, a second output drive transistor is turned on to drive the output node to a high supply voltage.

Abstract: A multi-phase power block for a switching regulator includes a phase control circuit, N power cells and a current sharing control circuit. The phase control circuit is configured to receive a single phase PWM clock signal and generate N clock signals in N phases. Each of the N power cells includes a pair of power switches, gate drivers, a control circuit receiving one of the N clock signals and generating gate drive signals for the gate drivers, and an inductor. The current sharing control circuit is configured to assess the inductor current at the inductor of the N power cells and to generate duty cycle control signals for the N power cells. The duty cycle control signals are applied to the control circuits to adjust the duty cycle of one or more clock signals supplied to the power cells to balance a current loading among the N power cells.

Abstract: A semiconductor device, circuit, and AC and DC load switch for maintaining a small input-output differential voltage and providing a defined response. The load switch can include a pass element coupled to an input terminal and an output terminal. The pass element can include a control terminal, with the control terminal controlling a response of the pass element. The load switch can include a first loop coupled to the control terminal configured to control a voltage drop between the input terminal and the output terminal while maintaining high impedance with the pass element. The load switch can include a second loop coupled to the control terminal configured to provide a defined filter response from the input terminal. The defined response can be a low pass response, high pass response, or a band pass response. The passband and/or stopband of the response can be programmed.

Abstract: In one embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and a secondary signal path including a pulse shaping stage incorporating a network and a scaling stage. The pre-emphasis circuit generates an overshoot pulse with variable pulse width. In another embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and one or more secondary signal paths incorporating a network implementing a specific transient response. Each of the secondary signal paths includes a scaling stage and a shaping stage each with programmable bias current. The scaling stage can be configured before or after the shaping amplifier. The pre-emphasis circuit generates an overshoot signal with variable amplitude and/or variable width.

Abstract: In one embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and a secondary signal path including a pulse shaping stage incorporating a network and a scaling stage. The pre-emphasis circuit generates an overshoot pulse with variable pulse width. In another embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and one or more secondary signal paths incorporating a network implementing a specific transient response. Each of the secondary signal paths includes a scaling stage and a shaping stage each with programmable bias current. The scaling stage can be configured before or after the shaping amplifier. The pre-emphasis circuit generates an overshoot signal with variable amplitude and/or variable width.

Abstract: A laser bias control and monitoring circuit receives a monitor diode current on an input node and generate a bias current for a laser diode on an output node where the monitor diode current flows into (positive polarity) or out of (negative polarity) the input node. The laser bias control and monitoring circuit includes a polarity independent current sensing circuit configured to receive the monitor diode current in either positive or negative polarity and to generate a normalized output current having a magnitude proportional to a magnitude of the monitor diode current. In this manner, the laser bias control and monitoring circuit can be used with laser diode and monitor diode combination in either the common anode or the common cathode configuration, or with the monitor diode current being provided from the anode or cathode of the monitor diode. No reprogramming or reconfiguration of the circuit is required.

Abstract: An energy efficient Ethernet physical layer (PHY) device including an EEE control module configured to generate a control signal to transition the PHY device into a low power consumption mode based an operating condition, and a pause frame generator module responsive to the control signals to generate a pause frame. The pause frame generator module is configured to send the pause frame to a media access control (MAC) device to reduce an incoming flow of data packets from the MAC device to the PHY device for a pause time duration. In operation, the pause frame generator module generates the pause frame including a pause time indicating the length of time for the PHY device to be in the low power consumption mode. The value of the pause time for each pause frame is determined adaptively based on the amount of data traffic to be transmitted from the PHY device.

Abstract: A transmission line pre-emphasis circuit includes a primary signal path receiving a digital data stream and generating a primary output current indicative of the digital data stream, one or more secondary signal paths each incorporating a network implementing a specific transient response where the one or more secondary signal paths receive the digital data stream and generate secondary output currents representing one or more overshoot signals indicative of the transient response of the respective network. The one or more secondary signal paths have variable gain being programmed through respective DC programming signals. The secondary output currents are summed with the primary output current. The transmission line pre-emphasis circuit further includes an output loading stage coupled to generate from the summed current a pre-emphasized digital output signal indicative of the one or more overshoot signals added to the digital data stream.

Abstract: A laser bias control and monitoring circuit receives a monitor diode current on an input node and generate a bias current for a laser diode on an output node where the monitor diode current flows into (positive polarity) or out of (negative polarity) the input node. The laser bias control and monitoring circuit includes a polarity independent current sensing circuit configured to receive the monitor diode current in either positive or negative polarity and to generate a normalized output current having a magnitude proportional to a magnitude of the monitor diode current. In this manner, the laser bias control and monitoring circuit can be used with laser diode and monitor diode combination in either the common anode or the common cathode configuration, or with the monitor diode current being provided from the anode or cathode of the monitor diode. No reprogramming or reconfiguration of the circuit is required.

Abstract: A single field photomask includes a first set of targets formed on a first side of the photomask, and a second set of targets formed on a second side of the photomask, opposite the first side. In operation, the photomask is to be applied to a wafer without any alignment marks. The photomask forms a first set of alignment marks in the wafer from the first set of targets, and the photomask further forms a second set of alignment marks in the wafer from the second set of targets. The first set of alignment marks is used to align to a first field mask and the second set of alignment marks is used to align to a second field mask to stitch an image of the first field mask to an image of the second field mask.

Abstract: A device for providing a high power, low resistance, efficient vertical DMOS device is disclosed. The device comprises providing a semiconductor substrate with a source body structure thereon. The device further comprises a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing.

Abstract: An integrated circuit capable of dual configuration of data flow and operable in a plurality of operational modes is provided. The circuit includes eight corner pins, wherein the eight corner pins comprise a first corner pin and a second corner pin on each side of the circuit in each of four side sets, wherein a first corner pin of one side of the circuit is proximate and adjacent to a second corner pin of an adjacent side counterclockwise from the first corner pin and together constitute a paired corner set, each paired corner set comprising a differential input and a differential output.

Abstract: A signal detection circuit for an Ethernet physical layer transceiver (PHY) device includes a first capacitor AC coupling a signal on the first receive terminal of the Ethernet PHY device to a first node; a second capacitor AC coupling a signal on the second receive terminal to a second node; re-biasing resistors for re-biasing the AC-coupled signals on the first and second nodes; first and second gain stages for amplifying the AC coupled signals; and a peak detect circuit. The peak detect circuit includes first and second diodes receiving the amplified signals from the gain stages to charge a peak detect capacitor. The signal detection circuit includes a comparator for comparing the voltage on the peak detect capacitor to a reference voltage and providing an output signal being indicative of the presence or absence of a signal on the first and second receive terminals of the Ethernet PHY device.

Abstract: A transmission line equalizer includes multiple signal paths connected in parallel between an equalizer input signal and an output amplifier where each signal path has a network implementing a specific frequency dependent response and each signal path implements current gain amplification with one or more of the signal paths having a variable gain programmed through a time invariant, DC programming signal. Furthermore, one or more of the signal paths implements linear-to-nonlinear signal transformations and compensating nonlinear-to-linear signal transformations to generate linearized output signals at the one or more signal paths. The equalizer further includes the output amplifier summing output signals from the multiple signal paths to generate an equalized output signal. In operation, the gain of the one or more signal paths is varied to establish the relative proportions of the output signals generated by each signal path and summed at the output amplifier.

Abstract: The present invention provides a current mirror circuit for matching current between two LEDs. The current mirror circuit includes a first sub-circuit, including a first transistor, a second transistor, and a first OPAMP, and a second sub-circuit including a third transistor, a fourth transistor, and a second OPAMP. The first sub-circuit is connected to a first LED and the second sub-circuit is connected to a second LED. The current mirror circuit also includes four switches which continuously switch the currents flowing through the first LED and the second LED to maintain a same average current through both the LEDs. This way, better current matching is achieved than possible using conventional current mirror circuits. The frequency of switching of currents is kept above the flicker perception of human eye, so that a person viewing the LEDs is unable to detect any changes in the illumination of the LEDs.

Abstract: A method of forming a lateral DMOS transistor includes performing a low energy implantation using a first dopant type and being applied to the entire device area. The dopants of the low energy implantation are blocked by the conductive gate. The method further includes performing a high energy implantation using a third dopant type and being applied to the entire device area. The dopants of the high energy implantation penetrate the conductive gate and is introduced into the entire device active area including underneath the conductive gate. After annealing, a double-diffused lightly doped drain (DLDD) region is formed from the high and low energy implantations and is used as a drift region of the lateral DMOS transistor. The DLDD region overlaps with the body region at a channel region and interacts with the dopants of the body region to adjust a threshold voltage of the lateral DMOS transistor.

Abstract: Input structures and topologies are provided for coupling a differential input into a first stage of a circuit, topology, or device. An input pin is coupled to an impedance divider that translates an input voltage to accommodate low input voltage levels, while not saturating an input differential pair. A termination pair with a center tap pin is further coupled to the input pins. The center tap facilitates coupling different termination configurations to the input signal. The topologies accommodate packaged devices that have at least three external pins, two pins for the coupling of a differential input signal, and a pin for the termination pair center tap.