Abstract: A flat-panel field emission display comprises a luminescent faceplate, a rigid backplate, and an interposed or sandwiched emitter or cathode plate. A dielectric connector ridge is screen-printed over the faceplate's rear surface. Upper and lower level conductors are then screen printed over the faceplate. The lower-level conductors are applied directly on the faceplate rear surface. The upper-level conductors are applied atop the connector ridge. A plurality of bond wire interconnections extend between individual screen-printed conductors of the upper and lower levels. The bond wire interconnections create inter-level electrical interconnections between said individual screen-printed conductors. The cathode plate is positioned over the connector ridge. The cathode plate has a plurality of die bond pads facing the faceplate rear surface and aligned with the upper-level conductors.

Abstract: A conductive, light-absorbing baseplate for use in a field emission display is disclosed. The interior surface of the baseplate is coated with a praseodymium-manganese oxide layer having a resistivity that does not exceed 1.times.10.sup.5 .OMEGA..multidot.cm. A field emission display is also disclosed which comprises the conductive, light-absorbing baseplate, as well as processes for manufacturing the baseplate, field emission display and the conductive, light-absorbing praseodymium-manganese oxide material used to coat the baseplate.

Abstract: The present invention teaches a field emission display ("FED") architecture for isolating display grids, wherein an FED has a plurality of pixels. Each of the pixels comprise at least two field emitter tips for displaying information to the pixel and a pixelator for driving the field emitter tips. Further, an isolated display grid is incorporated for each of the field emitter tips. Each display grids is coupled to a bus having a predetermined voltage by a link. In one embodiment of the present invention, the link can be disintegrated by internal or external means. In a second embodiment, the FED comprises a first and second bus, each of bus having a predetermined voltage, whereby a first isolated display grid is coupled to the first bus by a first link and a second isolated display grids is coupled to the second bus by a second link.

Abstract: A method of electrically testing pixel functionality is provided comprising releasably disposing a wafer in a socket. The wafer has at least one baseplate comprised of cathode emitters arranged in pixels. The socket has pads. The socket pads are contacted with test pins, and each of the pixels is addressed individually, thereby causing the cathode emitters to emit electrons in a current. The current is collected from each of the pixels on an anode screen. Alternatively, the anode card may have pins, and these pins contact pads on the baseplate. The baseplate, or substrate with baseplates, does not require a socket with pins.

Abstract: Binders, both inorganic and organic, are used for providing sufficient binding action to hold powder phosphor particles together as well as to the glass screen of a field emission display device.

Abstract: A driver circuit for driving the emitters of a flat panel display such as a field emission display. The driver circuit includes a capacitor and a charge circuit. The capacitor is connected between the emitter and an extraction grid held at a constant potential. The charge circuit has two inputs respectively connected to a row line and a column line. The charge circuit also has a charge terminal connected to the capacitor. In operation, the charge circuit applies at the charge terminal a selected voltage level which is below the grid voltage. The selected voltage level represents the intensity of the pixel associated with the emitter. In response to the selected voltage level at the charge terminal, the extraction grid charges the capacitor to a potential which is the difference between the grid voltage and the selected voltage level. When charged, the capacitor is isolated from the driver circuit. The charge stored in the isolated capacitor discharges through the emitter.

Abstract: According to an aspect of the present invention, a process is provided for manufacturing a field emission display. In one embodiment, the process comprises disposing a self-dimensioning support member between a backplate assembly and a die assembly, and positioning the die assembly and the backplate assembly relative to each other such that the self-dimensioning support member is dimensioned relative to the distance between the assemblies.

Abstract: Methods and apparatus for identifying and disabling shorted electrode pain (such as field emitter tip electrodes shorted to grid electrodes) in a field emission display by applying a test voltage across the two electrodes in each pair. The magnitude of the test voltage is set below the voltage required to initiate field emission from the emitter tip electrode. Because no field emission occurs at this voltage, the test voltage should produce no current flow through good (non-shorted) emitter tips. However, current will flow through emitter tips which are shorted to their respective grid electrodes. In one embodiment, the current flow vaporizes the bad emitter tips themselves. In another embodiment, the current flow thermally damages a removable link connected in series with either the shorted emitter tip or the shorted grid electrode.

Abstract: A method for controlling a field emission display to reduce emission to grid during turn on and turn off is provided. A field emission display (FED) includes emitter sites formed on a baseplate; a grid for controlling electron emission from the emitter sites; a display screen for collecting electrons to form an image and a power supply. In order to reduce emission to grid during turn on, the display screen is enabled by the power supply prior to enabling of the emitter sites. An anode-baseplate voltage differential is thus established prior to electron emission. For turn on, the method includes varying the capacitances of the control circuits for the display screen and grid such that a time constant (RC) for the grid is larger than a time constant (RC) for the display screen. Alternately the method of the invention can be implemented during turn on using software, using time delay circuit components, or using an emitter site control circuit to control electron flow to the emitter sites.

Abstract: A thin flat panel display is formed from two substrates uniformly spaced apart by a plurality of spacer members. The spacer members are formed into bundles, held together by binder material, and sliced into a plurality of thin discs. One opposing face of one of the substrates is provided with patterned arrays of first and second arrays of different adhesives. The discs are placed on the adhesives and processed to activate the adhesives, remove the binder and the second adhesive thereby reducing the number of spacers remaining in the assembly to only those adhered by the first adhesive. The second substrate is then juxtapositioned on the first substrate assembly and bonded thereto.

Abstract: A high resistance resistor for regulating current in a field emission display is integrated into circuitry of the field emission display. The resistor is in electrical communication with emitter sites for the field emission display and with other circuit components such as ground. The high resistance resistor can be formed as a layer of a high resistivity material, such as intrinsic polycrystalline silicon, polycrystalline silicon doped with a conductivity-degrading dopant, lightly doped polysilicon, titanium oxynitride, tantalum oxynitride or a glass type material deposited on a baseplate of the field emission display. Contacts are formed in the high resistivity material to establish electrical communication between the resistor and the emitter sites and between the resistor and the other circuit components. The contacts can be formed as low resistance contacts (e.g., ohmic contacts) or as high resistance contacts (e.g., Schottky contacts).

Abstract: Photoetchable glass is used to form spacer elements for large area field emission displays. Frit dots are placed onto a substrate. A sheet of photo etchable glass is exposed to UV light using a mask such that the UV light exposes the etchable areas and does not expose the areas which will form the spacers. The etchable glass is then heat treated to crystallize the UV exposed areas and to tailor the coefficient of thermal expansion. Next the glass is adhered to the frit coated substrate and the UV exposed areas etched away leaving spacers adhered to frit dots.

Abstract: A method for forming interelectrode spacers for flat panel display devices that employ reduced pressures, includes the steps of; forming a substrate out of an aerogel, xerogel photosensitive material (e.g., photosensitive glass, photosensitive aerogel, photosensitive xerogel); forming a pattern of openings and gas removal channels in the substrate; and then placing the substrate between a display screen and base plate of the display device. The substrate is formulated to be light weight, insulative and with a high compressive strength for resisting atmospheric loads placed on the display screen by the reduced pressure. In addition, the substrate is formulated to be easily etched, laser ablated or photochemically machined and assembled as a third member spacer structure.

Abstract: A method for evacuating and sealing a field emission display package is provided. The method includes forming a cover plate, a backplate, and a peripheral seal therebetween. The backplate is formed as a sub-assembly which includes a seal ring and a getter material. The seal ring includes compressible protrusions for initially separating the cover plate from the seal ring to provide evacuation openings. During a sealing and evacuation process the packages are placed in the reaction chamber of a furnace. The pressure in the reaction chamber is then reduced and the temperature is increased in a staged sequence. During the evacuating and sealing process the evacuation openings formed by the compressible protrusions provide a flow path for evacuation. As the sealing and evacuation process continues, the compressible protrusions and seal ring flow and commingle to form the peripheral seal. At the same time the getter material is activated and pumps contaminants from the sealed spaced formed within the package.

Abstract: A non-photolithographic, physical patterning process, which is useful for selectively etching of a substrate, is provided. The process comprises electrostatically charging liquid droplets which are selectively etchable with respect to the substrate, dispersing the droplets onto substrate in a pattern; and etching the substrate using the droplets as a mask.

Abstract: A method of manufacturing phosphor screens is disclosed. The method uses "sol-gel" for disposing a thin film of phosphor on a transparent substrate. The thin film of phosphor is applied in continuous form or in the form of an accurate dot pattern. The rastering of said dot pattern is performed either by screen printing before annealing the sol-gel, or by selective laser curing of a continuous thin film and washing off the non-cured portions. The phosphor screens are useful as monochrome or as full-color faceplates of field emission displays or cathode ray tubes.

Abstract: The present invention is directed to a novel etching process for a semiconductor material which inhibits corrosion of metal comprised of pretreating the material, preferably with a surfactant, and then exposing the material to a mixture comprising salt, a buffered oxide etch, and optionally a surfactant.

Abstract: A method of preparing a silicate-containing phosphor is provided. The method includes combining a mixture of metal or metalloid compounds with a gaseous silicon-containing in an amount sufficient to convert the compounds to silicates, and heating the silicates under conditions effective to form a phosphor.

Abstract: A mask and a method for forming a mask on a surface of an underlying layer of material used in semiconductor device manufacturing. The mask is a mixture of mask particles and spacer particles. The spacer particles space the mask particles apart from one another to control the distance and the uniformity of the distribution of mask particles across the surface of the underlying layer. The spacer particles and mask particles have different physical properties that allow the spacer particles to be selectively removed from the surface of the underlying layer. The spacer particles are preferably removed from the surface of the underlying layer by selectively etching the spacer particles from the underlying layer. After the spacer particles are removed from the underlying layer, the mask particles remain on the underlying layer to provide spaced apart mask elements on the surface of the underlying layer.

Abstract: A method for forming an electrical connection between a semiconductor die and a corresponding electrical component mounted within an electrical device is provided. The method includes wire bonding metal wires to the bond pads of the die and then severing the metal wires to form loose leads attached to the bond pads. With the die mounted to the electrical device, the loose leads are bonded to the electrical component using a bonding tip. In an illustrative embodiment, the electrical device is a field emission display package and the electrical component is conductive traces for the package. Advantageous, the method can be used to form the electrical connection between the die mounted in a sealed space and the corresponding electrical component which is outside of the sealed space.