Abstract: A method for etching structures having topography, which structures are comprised of polysilicon disposed over an oxide, by placing an electrostatic shield on a high density source etcher while etching the structures. The etch involves the removal of the polysilicon which overhangs the oxide structure below it, thereby substantially eliminating conductive stringers.

Abstract: An integrated circuit of the present invention includes power regulating circuitry for reducing preregulator bias current. In one embodiment, power regulating circuitry includes a two stage preregulator for supplying current to a charge pump and a primary regulator. The first stage includes a high power operational amplifier for quickly establishing substrate bias and other pumped voltages before primary voltage is coupled to the remainder of the integrated circuit. Preregulated and pumped voltages are used to establish a reference voltage for the primary regulator. The second stage preregulator includes a low power series regulator to power the charge pumps and so maintain the reference voltage. When the primary regulator has generated the primary voltage level, the power regulating circuitry couples the primary voltage to the remainder of the integrated circuit and disables the first stage preregulator.

Abstract: This invention is a look-ahead method for determining optimum production schedules for each production step based on factory-wide monitoring of in-process part queues at all potential production bottlenecks. For each product having associated therewith a throughput bottleneck, a maximum queue quantity Q.sub.MAX and a minimum queue Q.sub.MIN quantity are assigned. When a machine completes a lot of a particular product at a production step P that proceeds the bottleneck step B, the look-ahead method is initiated. The queue at step P is searched and the next lot to be processed is selected. If that lot is a product for which Q.sub.MAX and Q.sub.MIN values have been assigned at step B, then the queue quantity at step B is determined. If, on one hand, the queue quantity at step B is less than Q.sub.MAX, or between Q.sub.MAX and Q.sub.MIN and the queue quantity is climbing upward from a sub-Q.sub.MIN value and has not yet exceeded its Q.sub.MAX value, then the lot is processed without further analysis.

Abstract: A method and structure for a programmable read-only memory comprises a thin gate oxide over a source region and a thick gate oxide over the drain region. A semiconductor substrate is lightly doped and has regions of thin sacrificial oxide overlying what will become the transistor channel, source, and drain, and thick field oxide. The region that will become the transistor source is protected with photoresist, and the drain region and a portion of the channel is doped, for example, with boron. The resist and sacrificial oxide is stripped, and gate oxide is formed from the exposed silicon substrate. The more heavily doped drain and channel regions oxidize at a faster rate than the lightly doped source region, and thus the gate oxide formed is thicker. Floating and control gates are formed over the channel region, covering both the thicker and thinner gate oxide.

Abstract: A test system is added to a substrate and a test mode of operation is added to the timing and control functions of a system on the substrate. When a multifunctional system on the substrate is tested, a first functional subsystem is connected to an external tester. The tester causes the timing and control system to enter the test mode of operation. When in the test mode of operation, the test system provides a signal derived from a signal generator on the substrate. The generated signal is coupled to a second functional subsystem so that functional independence of the first and second subsystems can be verified.

Abstract: A module such as a SIMM or other type of memory module is provided with supply power at a higher potential than the operating potential of semiconductor memory devices on the module. A voltage regulator circuit on the module reduces the potential supplied to the memory devices and provides the power to the memory devices at regulated potential than would be achieved by providing the supply power at the desired potential in the first place. Advantages include reduction in error rate, even when semiconductor components are used which are unusually susceptible to variations in supply potential.

Abstract: This invention is a process for fabricating a CMOS dynamic random access memory (DRAM) wherein a high-energy, oblique P-type implant is employed for punchthrough protection and field isolation enhancement or alternatively for punchthrough protection and as the sole field isolation implant. The process proceeds by forming P-type and N-type regions in a silicon substrate, performing an optional field isolation implant and forming field isolation regions using LOCOS or a modified LOCOS sequence, forming a gate dielectric layer, forming wordlines, depositing an offsetting dielectric layer, performing a low-dosage N-type implant in N-channel source/drain regions, forming spacers on the sidewalls of the gate electrodes, constructing cell capacitors superjacent the storage-node regions, performing a high-energy oblique implant with a P-type impurity which penetrates the spacers and field oxide layers, and performing a high-dosage N-type implant in bitline contact regions.

Abstract: A process for forming field oxide on a semiconductor substrate having reduced field oxide thinning comprises forming an oxide layer over a semiconductor substrate, and forming a protective layer over the oxide layer. A mask is formed over the protective layer thereby forming exposed and covered regions of the protective layer. The exposed portions of the protective layer are removed to form at least first, second, and third disconnected protective structures, wherein the distance between the first and second protective structures is smaller than the distance between the second and third protective structures. The oxide layer and a portion of the substrate between the protective structures is removed to expose a portion of the substrate. A blanket polycrystalline silicon (poly) layer is formed over the substrate, and the poly layer is isotropically etched to remove the poly from between the second and third protective structures and to leave a portion of the poly between the first and second structures.

Abstract: High quality silicon thin films are formed on a substrate in a conventional chemical vapor deposition reactor using silicon hydride source gas, and allowing adsorption of the deposition at low temperature before decomposition at a higher temperature. The silicon source gas comprises a mixture of silane and polysilanes exhibiting different coefficients of adsorption in order to achieve a uniform growth of successive thin films.

Abstract: A signal-delaying capacitive circuit applied to a node in a microcircuit device is immunized against the variation of the supply voltage by a metal-oxide semiconductor connected in series between the node and the signal-delaying capacitive circuit. The gate of tile semiconductor is biased with a voltage signal proportional to the supply voltage, whereby the resistance of the semiconductor is increased as the supply voltage decreases; thus, isolating the capacitive circuit from the node and reducing the delay.

Abstract: The present invention teaches a method for reducing sheet resistance in the fabrication of semiconductor wafers. A silicon substrate having a gate oxide layer thereon is provided in a chamber. Subsequently, a polysilicon layer is formed superjacent the gate oxide layer in situ by exposing the silicon substrate to a first gas comprising at least one of silane, disilane, and dichlorosilane, and radiant energy at a temperature substantially within the range of 500.degree. C. to 1250.degree. C. for at least 10 seconds. The polysilicon substrate can be doped with a material such as phosphorus, arsenic and boron for example, by exposing the polysilicon to a second gas under the stated conditions. A conductive layer comprising at least one of tungsten silicide (WSi.sub.x) and titanium silicide (TiSi.sub.x) can be formed superjacent the polysilicon by exposing the polysilicon to a third gas comprising at least one of WF.sub.6, TMAT and TiCl.sub.4.

Abstract: In a microcircuit device such as a memory chip, where a bank of fuse-controlled latch pulse routing-circuits are used to program redundant circuits or other programming options with every memory cycle or multiple thereof, the amount of current drawn by every fuse-control circuit is reduced by controlling each bank of circuits with a bank-enabling, fuse-programmed circuit between the latch pulse source and the bank of fuse-controlled programming circuits, and by adding a second fuse into each programming circuit; whereby, the bank of programing circuits can be enabled by alternately blowing one of two fuses in the bank-enabling circuit, and each programming logic can set by alternately blowing one of its pair of fuses thus cutting off any current path through the programming circuit regardless of the programming state of the circuit.

Abstract: A new and improved static random access memory (SRAM) cell wherein separate regions of polysilicon are formed over a silicon substrate and are separated by defined openings therein into which oxide filler material is introduced to render the regions of polysilicon and oxide substantially co-planar at their upper surfaces. An access transistor and a thin film load transistor are formed within and adjacent to first and second regions of the polysilicon, respectively, and yet a third, pull down transistor is formed within and adjacent to a third polysilicon region. The thin film transistor includes a thin second layer of polysilicon which is electrically isolated from the second one of the polysilicon regions and is doped to form therein source, drain and channel regions. Advantageously, the thin film transistor is formed on this substantially planar surface, thereby improving process yields and device performance.

Abstract: The invention is a method for creating a portion of an integrated circuit on a semiconductor wafer. The invention comprises doping a substrate to form a doped well region having an opposite conductivity type than the substrate. Separate photomasking steps are used to define N-channel and P-channel metal oxide semiconductor (MOS) transistor gates. A trench is formed near the well without using additional masking steps. The trench improves the latch up immunity of the device. The invention is also the apparatus created by the method and comprises a trench positioned in the substrate to interrupt the conduction of minority carriers between two regions of the substrate. Thus, the invention improves latch up immunity without additional process complexity.

Abstract: An embodiment of the present invention depicts a storage capacitor comprising: a bottom plate structure having a hemispherical grain silicon surface; a titanium nitride layer adjacent and coextensive the hemispherical grain silicon; an insulating layer adjacent and coextensive the titanium nitride layer; and a top plate structure comprising conductively doped polysilicon layer superjacent and coextensive the insulating layer.

Abstract: A process for semiconductor manufacture in which the top corners of conductive features are preferentially etched compared to the etch rate of the vertical and horizontal surfaces, thereby creating a sloped (prograde) profile, i.e., facets. The material removed through the sputter etch process is oxidized and redeposited along the sides of the feature and along the surface of the substrate, thereby improving step coverage when a subsequent dielectric layer is deposited thereon.

Abstract: This invention constitutes a process for fabricating a structure which, when incorporated in an integrated circuit, will reduce current leakage into the substrate from transistor source/drain regions. The structure is particularly useful in dynamic random access memories, as it will minimize the effect of alpha particle radiation, thus improving the soft error rate. A trench is etched through the transistor source or drain region. A high dosage of oxygen ions is then implanted at low energy in the floor, but not the sidewalls of the trench. The resulting oxygen-implanted silicon layer at the bottom of the trench is then converted to a silicon dioxide barrier layer through rapid thermal processing or furnace annealing in an inert ambient. The trench is then lined with a deposited contact layer that is rendered conductive either during or subsequent to deposition. Contact between the contact layer and the source or drain region is made through the sidewalls of the trench, which were not implanted with oxygen.

Abstract: A circuit, responsive to the application of primary power, generates signals to establish the initial state of a logic circuit. Generated signals are interposed on the logic circuit's input signal line until initialization is complete. After initialization, the logic circuit's input signal line is recoupled for normal operation.

Abstract: An improved programmable logic device (PLD) having a macrocell operable in a registered mode is disclosed. The improved PLD has exclusive lines for both registered feedback and for external input, both of which are fed into a single multiplexer. The output of the multiplexer is fed into the PLD's AND array. The external input line is coupled to the I/O terminal of the macrocell. A tri-state output buffer selectively decouples the I/O terminal from the macrocell output so that the I/O terminal may be employed to alternately receive a registered output signal from the macrocell or to send an external control signal to the AND array.

Abstract: The invention is a circuit and method for maintaining a negative potential, with respect to the digit line potential, on non-selected wordlines.