Abstract: A method of chemical vapor depositing a layer on a semiconductor wafer includes: a) positioning a semiconductor wafer within a chemical vapor deposition reactor; b) providing an organometallic reductive elimination precursor source in a non-gaseous form, the non-gaseous organometallic precursor compound containing at least two ligands bonded to a linking atom; c) subjecting the non-gaseous organometallic reductive elimination precursor to temperature and pressure conditions which vaporize the non-gaseous organometallic reductive elimination precursor into a source gas, and providing the source gas into the chemical vapor deposition reactor having the semiconductor wafer positioned therein; d) subjecting the source gas to reactive conditions within the reactor effective to impart a reductive elimination reaction of the precursor which reduces the linking atom from the precursor and which oxidizes the ligands to generate gaseous molecules having all atoms in a closed shell, non-ionic configuration, with the gas

Abstract: A process for suppressing hot electrons in sub half micron MOS devices wherein a gate oxide and a gate electrode are formed on the surface of a silicon substrate and source and drain regions are ion implanted into the silicon substrate using the gate electrode as a mask. The process includes forming a layer of silicon dioxide over the gate electrode and over the source and drain regions of the substrate, and then introducing a barrier layer forming element into the layer of silicon dioxide to form a thin barrier region to hot electrons at the interface between the silicon substrate and the silicon dioxide. In a preferred embodiment of the invention, nitrogen is introduced into the silicon dioxide by heating the wafer in a rapid thermal processor and in the presence of a nitrogen containing gas at an elevated temperature for a predetermined time. The nitrogen containing gas may be selected from the group consisting of nitrogen trifluoride, ammonia and nitrous oxide.

Abstract: A deposition method of reducing fixed charge in a layer of silicon dioxide includes: a) providing a gaseous organosilicon compound to a chemical vapor deposition reactor having a semiconductor wafer positioned therein; b) providing an oxidizing gas to the reactor for reaction with the organosilicon compound; c) feeding a gaseous hydrogen containing source to the reactor; and d) reacting the organosilicon compound, oxidizing gas and gaseous hydrogen containing source to deposit a layer of silicon dioxide on the wafer, the hydrogen containing source gas effectively reacting with the organosilicon compound to produce reduced fixed charge in the deposited silicon dioxide layer over that which would be present if no hydrogen containing source gas were fed to the reactor under otherwise identical reacting conditions.

Abstract: A method is disclosed for reducing the effects of semiconductor deformities. Initially, a semiconductor substrate is provided. The substrate has at least one layer superjacent the substrate and at least one layer subjacent the substrate. Subsequently, the semiconductor structure is examined for warp and bow type deformities. As a result of this examination, the warp and bow measurements of the semiconductor structure are compared with a reference. In the event that the measured warp and bow exceed a predetermined tolerance, either the thickness of the layer superjacent or the thickness of the layer subjacent is reduced. This reducing step can be accomplished by chemical and/or mechanical planarization, dry etching, wet etching or plasma etching.

Abstract: The invention is a storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode comprising a barrier layer interposed between a conductive plug and an oxidation resistant layer. A layer of titanium silicide is fabricated to lie between the conductive plug and the oxidation resistant layer. A thick insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant. The method comprises forming the conductive plug in a thick layer of insulative material such as oxide or oxide/nitride. The conductive plug is recessed from a planarized top surface of the thick insulative layer. Titanium is deposited and a rapid thermal anneal is performed. The titanium reacts with silicide of the conductive plug to form TiSi at the bottom of the recess. Unreacted Ti is removed. The barrier layer is then formed in the recess.

Abstract: There is a hardware implemented row copy operation mode for a DRAM to relieve the VRAMs from this slower repetitive operation. In addition, by providing circuitry that will generate a solid repetitive pattern for the full or portions of the screen. Another advantage of the invention occurs during testing of a DRAM with this circuitry. By having the ability of filling the memory array with, for example all digital ones in each cell, the quality of the die can easily be tested by modifying individual cells with a digital zero. Uniquely, this circuitry relieves the testing circuitry from filling in a background of information like the all ones background. Another feature of the invention allows graphic cards that exclusively use DRAMs, to eliminate the additional circuitry needed to perform the row copy feature, or creation of backgrounds.

Abstract: The present invention teaches a memory comprising an array of memory cells. Each cell of the array in the memory comprises a bus, and a diode, preferably a zener diode, having a substantially low breakdown voltage. Further, each cell comprises a programmable element, preferably an antifuse, for selectively coupling the diode with the bus.

Abstract: An improved method and apparatus are provided for subliming solid precursors, and especially organometallic precursors, for use in a chemical vapor deposition (CVD) process. The sublimation apparatus includes a sealed vessel having a vacuum chamber. A quantity of the solid precursor is mixed with a loosely packed particulate material, such as ceramic beads, placed within the vacuum chamber. The vacuum chamber and particulate material are heated. A supply of a carrier gas is directed through the particulate material (particularly through pockets formed in the particulate material) to sublime the precursor which coats the individual particles of particulate material. By agitating the particulate material, a relatively constant sublimation area is maintained. Agitation of the particulate material may be with a mechanical stirrer or by directing an a.c. field through a piezoelectric particulate material.

Abstract: The invention is a semiconductor memory structure having an electrically conductive substrate interconnect formed to provide electrical continuity between a buried contact region and a source/drain region of a transistor without overlap of the buried contact region with the source/drain region. The electrically conductive substrate interconnect is formed during an ion bombardment of the substrate wherein the ions enter the substrate at an oblique angle and underlie at least a portion of a region utilized to control the amount of ions entering the substrate.

Abstract: An improved method of fabricating phase shifting masks for semiconductor manufacture includes protecting an opaque layer of the mask during the mask fabrication process with a toughened layer of resist. For forming a Levenson phase shifting mask, an opaque layer is deposited on a transparent substrate. The opaque layer is then patterned using a layer of resist. This layer of resist is toughened and de-sensitized to subsequent patterning and intermediate processing. A phase layer of resist is then deposited on the toughened layer of resist and patterned for etching phase shifting areas in the substrate. During the etching process the opaque layer is protected by the toughened layer of resist. Etching of the phase shifting areas on the substrate can be in stages using a voting technique.

Abstract: An improved N-channel field-effect transistor is fabricated by performing a vertical N- implant, aligned to the vertical edges of the gate electrode, in both the source and drain regions of the device. In a first embodiment of the invention intended for use in dynamic random access memory access devices, a dielectric spacer is then formed on the sidewall of the gate electrode adjacent the drain (i.e., the regions which functions as the bitline contact in a DRAM memory cell). A vertical N+ implant, aligned to the exposed vertical edge of that spacer, is performed, in addition to an oblique implant of an N-type impurity. The oblique implant dosage is significantly greater than the N- implant dosage, but significantly less than the N+ implant dosage.

Abstract: A semiconductor wafer is washed in a dilute phosphoric acid solution after the metal features have been patterned and etched, thereby removing substantially all of the residual oxide, chlorine, and/or fluorine contamination which remains on the features. This will substantially eliminate corrosion of the features. The phosphoric acid wash also substantially prevents voids from forming during a subsequent alloy step. The features can include bond pads, vias, contacts, interconnects, etc.

Abstract: The present invention is a Static Random Access Memory fabrication process for forming a buried contact, by the steps of: patterning a photoresist layer over the field silicon dioxide regions and the spaced apart areas of the substrate, thereby providing a buried contact implant window to expose a portion of at least one spaced apart area and an adjacent field silicon dioxide end portion; implanting an N-type dopant through the buried implant contact window, the implant forming a first N-type diffusion region in the exposed spaced apart area and changing the etch rate of the exposed field silicon dioxide end portion; stripping the masking layer; growing a sacrificial silicon dioxide layer, over the field silicon dioxide regions and the spaced apart areas of the supporting silicon substrate, thereby annealing the exposed field silicon dioxide end portion and returning the etch rate of the exposed field silicon dioxide end portion to substantially the same etch rate as prior to the implantation step; stripping

Abstract: A method for fabricating semiconductor wafers is disclosed, wherein a semiconductor substrate is provided in a chamber. Subsequently, a first silicon nitride layer is formed in situ under high pressure superjacent the substrate by introducing a gas containing nitrogen, preferably NH.sub.3 combined with N.sub.2, at a temperature within the range of 850.degree. C. to 1150.degree. C. for approximately 10 to 60 seconds. This results in the first layer having a thickness in the approximate range of 5 .ANG. to 30 .ANG.. A semiconductor film is then deposited in situ under high pressure superjacent the first silicon nitride layer, preferably by means of Rapid Thermal Processing Chemical Vapor Deposition ("RTPCVD"). In an alternate embodiment of the present invention, this is accomplished by either Low Pressure Chemical Vapor Deposition ("LPCVD") or Molecular Beam Epitaxy ("MBE"). The thickness of the film is in the approximate range of 10 .ANG. to 40 .ANG..

Abstract: In an integrated microcircuit device the supply voltage is monitored by a pair of threshold detector logic circuits configured to generate a first control signal when said supply voltage crosses over a minimum level, and a second control signal when said supply voltage crosses over a maximum level. The control signals are used to configure the device into distinct modes of operation, whereby the functions of the device and the voltage level of the power supply applied to them during testing or operation may be controlled by varying the supply voltage.

Abstract: A method for reducing the effects of buckling, cracking, or wrinkling in multilayer heterostructures is provided. The method involves forming a planarization layer superjacent a semiconductor substrate. A barrier film having a structural integrity is formed superjacent the planarization layer by exposing the substrate to a gas and radiant energy. A second layer is formed superjacent the barrier film. The substrate is heated to cause the planarization layer to expand according to a first thermal coefficient of expansion, the second layer to expand according to a second thermal coefficient of expansion, and the structural integrity of the barrier film to be maintained. This results in the barrier film isolating the planarization layer from the second layer, thereby preventing the planarization layer and the second layer from interacting during the heating step. Further, it enables the planarization layer to go through a solid state reaction and the second layer to obtain a uniform reflow.

Abstract: A memory in which a portion of a digit line is isolated from the remainder of the digit line during a write cycle has improved performance. In the conventional architecture of a memory device, cells are arranged in rows and columns and a sense amplifier is employed for a pair of columns, located between a pair of complementary digit lines. An embodiment of the present invention in this architecture provides improved means for isolating the sense amplifier during a write cycle.

Abstract: Disclosed is a technique for testing a singularized semiconductor die prior to packaging the die, thereby allowing for the packaging or other use of only known good die. The invention employs a carrier tray which preferably supports several die carriers which individually support a plurality of dies. Bridge clamps press against rigid covers which bias the dies against the contact members. The die carriers include a housing of ceramic or other workable material. Contact pads on the interior of the package are coupled to exterior leads with conductive traces. The back side of a semiconductor die to be tested is removably mounted to a lid, and the bond pads on the die are aligned with the contact pads on the interior of the package. The lid is attached to the package thereby electrically coupling the contact pads with the bond pads on the die. The package has a configuration which facilitates the handling of the carrier so that the carrier can be conveniently used during burn-in and test procedures.

Abstract: This invention is an improved pull-up circuit for P-channel sense amplifiers in dynamic random access memory arrays having non-bootstrapped wordlines. The improved pull-up circuit features a voltage-comparator-controlled P-channel device which couples the power supply bus to a pull-up node for high current flow to the node and to digit lines which are coupled to the node via P-channel isolation devices. During the pull-up cycle, the P-channel device remains "on" as long as a reference voltage is greater than a variable voltage which represents the voltage level on portions of the digit lines farthest from the P-channel sense amplifier. The pull-up circuit also has an N-channel device which couples the power supply node to the pull-up node for maintenance of a desired voltage level equal to V.sub.cc minus the threshold voltage of the N-channel device.

Abstract: There is an output buffer which reduces the amount of voltage bounce occurring during the switching of the outputted signal. Uniquely, there is an output buffer/driver which turns on either driver transistor by progressively increasing the voltage on the control gates in a series of steps. Additionally, and simultaneously, the complementary signal is turned off immediately to prevent any possibility of creating current crossing in the output driver. Additionally, the invention has the advantage of avoiding cross current from occurring during switching of the output signals.