Abstract: A system is disclosed for externally measuring the temperature of a substrate having a reflective surface within a chamber. The system comprises a first light source having sufficient intensity for bombarding the reflective surface with photons, thereby heating the surface. The first light source has an output level and a wavelength substantially in the absorption band of silicon. The system also comprises means for exposing the substrate to a gas in order to form a layer superjacent the reflective surface. A sensor, preferably a photo detector, for sensing changes in the reflectivity of the surface is included. In one embodiment of the present invention, the sensor comprises a second light source and a sensor, for sensing the reflectivity of the surface caused by the reflecting photons. Furthermore, the system comprises control circuitry for controlling the first light source in response to the sensor; the control circuitry being coupled to the sensor by a feedback loop.

Abstract: The method of the present invention introduces a fabrication method for forming a storage capacitor on a supporting silicon substrate of a semiconductor device, by the steps of: forming a bottom capacitor electrode comprising conductively doped polysilicon; forming an insulating layer over the bottom electrode via a first rapid thermal processing step (RTP) using rapid thermal silicon nitride (RTN); forming a capacitor dielectric material comprising tantalum oxide (Ta.sub.2 O.sub.5) over the insulating layer; forming a semiconductive layer comprising polysilicon over the capacitor dielectric material; converting the semiconductive layer into a reaction prevention barrier by subjecting the semiconductive layer to a second rapid thermal processing step (RTP) using rapid thermal silicon nitride (RTN); and forming a top capacitor conductive electrode comprising titanium nitride (TiN) over the reaction prevention barrier.

Abstract: The basic concept of the present invention comprises converting a standard buffer circuit into an adjustable buffer circuit that will in effect reduce the operating speed and power consumption of the IC in which it is constructed. An adjustable buffer circuit can be designed into a chip design that will allow manufacturing to either use a bonding option or the blowing of a fuse to adjust its operating speed and active power consumption. One important application would be in memory devices such as for static random access memory (SRAM) devices. For example, if may be desirable to allow a -15 ns access time SRAM to be downgraded to a -20 ns or -35 ns access time device while lowering its active power consumption by .apprxeq.20-30% so that it will pass the -35 ns I.sub.CC specification rating.

Abstract: A method and system for fabricating semiconductor wafers is disclosed wherein an atomically clean, semiconductor substrate having a surface is provided in a rapid thermal processing chamber. One embodiment involves cleaning the substrate by exposing it to a first gas at a temperature substantially within the range of 850.degree. C. to 1250.degree. C. for approximately 10 to 60 seconds. Subsequently, a coating having a first thickness is formed superjacent the substrate surface by introducing a second gas at a temperature substantially within the range of 850.degree. C. to 1250.degree. C. for approximately 5 to 30 seconds in the chamber. The resultant coating, depending on the gas selected, comprises either SiO.sub.2 or Si-F.Subsequently, the substrate having the coating is exposed to a third gas at a temperature substantially within the range of 900.degree. C. to 1050.degree. C. for approximately 30 minutes to one hour, thereby forming a silicon dioxide layer.

Abstract: Active regions on a semiconductor substrate are isolated, whereby an Oxide/Nitride/Oxide sandwich is disposed on a substrate, and a polysilicon layer and a nitride layer are also disposed thereon. The Oxide/Nitride/Oxide sandwich substantially inhibits "pitting" of the substrate when the polysilicon layer is removed.Method of preventing "pitting" of an underlying substrate through the use of a nitride (or other HF-resistant material) disposed beneath the polysilicon layer of a Poly Buffered LOCOS stack.

Abstract: A method of erasing, programming, and verifying a flash electrically erasable programmable read-only memory where all cells are first erased to a high threshold voltage, preferably by simultaneous Fowler-Nordheim tunnelling, and then selected cells are programmed to a low threshold voltage using Fowler-Nordheim tunnelling. Programming is achieved by applying a negative voltage to the selected wordline and applying a positive voltage to the selected bitline. Only those cells which have both the wordline and bitline selected will have sufficient wordline-to-bitline voltage difference to cause programming. A key advantage of this new method is that a verification (read) procedure can be used to monitor for the desirable tight distribution, low threshold voltage V.sub.t on programmed cells and re-program only those cells which have a V.sub.t higher than the desired V.sub.t.

Abstract: The present invention provides a method for forming conductive container structures on a supporting substrate of a semiconductor device, by: forming an insulating layer over parallel conductive lines and existing material on the surface of the supporting substrate; providing openings into the insulating layer, the openings forming vertical sidewalls in the insulating layer that resides between two neighboring conductive lines and thereby exposing an underlying conductive material; forming a sacrificial layer that makes contact with the underlying conductive material; forming a barrier layer overlying and conforming to the sacrificial layer; forming insulating spacers on the vertical sidewalls of the barrier layer; removing portions of the barrier layer and the sacrificial layer that span between the insulating spacers to thereby expose a portion of the underlying conductive material; removing the insulating spacers and thereby exposing the barrier layer; forming a conductive layer that conforms to the exposed

Abstract: A signal-delaying capacitive circuit applied to a node in a microcircuit device is immunized against the variation of the supply voltage by a metal-oxide semiconductor connected in series between the node and the signal-delaying capacitive circuit. The gate of the semiconductor is biased with a voltage signal proportional to the supply voltage, whereby the resistance of the semiconductor is increased as the supply voltage decreases; thus, isolating the capacitive circuit from the node and reducing the delay.

Abstract: A method is disclosed for continuously measuring the temperature of a semiconductor substrate in a chamber is disclosed. The first step of the method involves providing a substantially clean semiconductor substrate having a layer a reflective surface thereon into a chamber. A film is formed superjacent the surface by introducing a gas comprising at least one of N.sub.2, NH.sub.3, O.sub.2, N.sub.2 O, Ar, Ar--H.sub.2, H.sub.2, GeH.sub.4, or any fluorine based gas and photon energy in situ. The photon energy, having a wavelength substantially in the absorption band of silicon, generates a temperature substantially within the range of 500.degree. C. to 1250.degree. C. Subsequently, the reflectivity of the surface is measured prior to introducing the gas, and continuously, while forming the film until the film is substantially formed. The substrate is exposed to photon energy having a power level responsive to the measured reflectivities of the film.

Abstract: Improved polymer batteries and improved methods of manufacturing such polymer batteries are provided. One improved method of manufacture involves the formation of a laminated array structure that includes a number of individual battery cells. After formation of the laminated array the individual batteries are singulated from the array by cutting, shearing or stamping. Other manufacturing improvements include the use of a printing process (e.g. stenciling) to form the cathodes, the use of permanent mask layers to contain and insulate the cathodes and anodes, and the use of a molten lithium deposition process for forming the anodes.

Abstract: An improved method for teaching the location of a bond site on a selected lead finger of a semiconductor leadframe during a wire bonding process is provided. Initially, the location of the lateral edges and terminal edge of a tip portion of the lead finger is sensed by an automated vision system of a wire bonding apparatus. A width (W) and a longitudinal axis of the lead finger are then determined. The bond site is located along the longitudinal axis a predetermined distance of (W/2) from the terminal edge of the lead finger. The improved method allows greater accuracy in the placement of bond sites and precisely controls the length of the bond wire used during the wire bonding process.

Abstract: An electric interconnection method includes: a) providing two conductive layers separated by including material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Abstract: A memory device includes an output buffer for temporarily storing first and second data that are sequentially retrieved from a memory array during a read cycle. The output buffer holds the first data until it is replaced by the second data. A pulse circuit is connected to the memory array and output buffer, and is designed to generate a pulse signal as soon as data becomes valid. The pulse signal causes the output buffer to replace the first data with the second data and to latch the second data therein until receipt of the next data. The pulse circuit generates the data valid signal upon receipt of the column address strobe and the presence of data on the data I/O lines. A method for outputting data from the memory device is also described.

Abstract: There is an IC (integrated circuit) testing device 11 that receives singulated ICs from a singulation station's bottom table 44, where an IC 15 has slid down onto loading ramp or track 16. The IC will slide into test station 18, where stop pin 22 has been inserted to stop the IC in DUT (device under test) station 20. In the DUT station, the IC is securely held in position by an extractor bar 26, insertion bar 28, and a part guide 24. Thereby, test cite station 18 will move downward and insert IC 15 into testing socket 30. After testing the IC, testing station 18 returns upward with the IC in the same secured position. Pin 22 will be removed to allow the IC to slide into part holding station 31. If the IC was not defective, pin 32 will be removed to allow the IC to slide onto track 36 of the IC separator station 34. While the test cite station 18 is in the up position a second IC is slid along track 16 and loaded into DUT cite 20 being readied for the next test cycle.

Abstract: A process to create a faceted (prograde) profile for an integrated circuit, in which the top corners of a layer disposed over a feature are preferentially etched, thereby creating slopes. The profile which results from the deposit of subsequent layers is more easily etched as a result of the contour imparted by the faceted edges. Since the subsequent layers are placed in the "line of sight" of the etch plasma, there are significantly fewer "stringers.

Abstract: The present invention is a process for providing a planarized transistor gate on a non-planar starting substrate, by depositing a layer of planarized conductive polysilicon material overlying neighboring field oxide isolation regions such that the height of the conductive polysilicon material extends above the topology of the field oxide isolation regions; depositing a layer of conductive silicide material superjacent and coextensive the conductive polysilicon material; and then patterning the planarized conductive polysilicon material and the conductive silicide material thereby forming the planarized transistor gate.

Abstract: A new inverting output driver circuit is disclosed that reduces electron injection into the substrate by the drain of the circuit's pull-up field effect transistor. This is accomplished by adding additional circuitry that allows the gate voltage of the pull-up transistor to track the source voltage. The output circuit makes use of an inverter having an output node (hereinafter the intermediate node) coupled to V.sub.CC through a first P-channel FET, and to ground through first and second series coupled N-channel FETs, respectively. The gates of the P-channel FET and the first N-channel FET are coupled to and controlled by an input node. The inverter output node controls the gate of third N-channel FET, through which a final output node is coupled to V.sub.CC. The intermediate node is coupled to the final output node through a fourth N-channel FET, the gate of which is held at ground potential. The gate of the second N-channel FET is coupled to V.sub.

Abstract: In semiconductor manufacture, a method of etching a polysilicon layer to a gate oxide in a semiconductor structure is provided. The method is performed insitu in a plasma etch chamber. Initially, an oxide hard mask is formed on the semiconductor structure by etching a deposited oxide layer through a photoresist mask. The photoresist mask is then stripped in the same etch chamber using a high pressure ozone plasma. With the photoresist mask stripped from the semiconductor structure, the polysilicon layer can be etched through the oxide hard mask to the gate oxide with a high etch selectivity.

Abstract: This invention is a low-power circuit for detecting and latching the state of a fusible link. During a power-up sequence, the circuit makes a one time determination regarding the blown or unblown status of a fuse element. In one embodiment of the invention, the circuit comprises a fuse detect node which is coupled to power supply voltage (V.sub.cc) through a first IGFET and to ground through a second IGFET (which, in this embodiment, has more drive than the first) and the fuse element, respectively, when the fuse element is not severed. In another embodiment of the invention, the fuse detect node is coupled to ground through the second IGFET, and to power supply voltage (V.sub.cc) through the first IGFET (which, in this embodiment, has more drive than the second) and the fuse element, respectively, when the fuse element is not severed.

Abstract: The present invention provides production repeatable process to form polysilicon storage node structures using MVP technology. The storage node is formed over word lines beginning with a deposition and planarization of an insulator or composite insulator. A contact/container photo and etch creates a contact/container opening to provide access to the underlying active area either directly or through a conductive plug. After the contact/container opening is formed, an insitu doped polysilicon layer is deposited and planarized to completely fill contact/container opening while isolating adjacent storage nodes from one another. Next an oxide layer is deposited and is followed by deposition of HSG poly. Then a plasma poly etch of the HSG poly is performed that is followed by a plasma oxide etch. After these steps, a timed poly etch is performed long enough to sufficiently transfer an `archipelago` pattern to storage node poly.