Abstract: A neutralization of an equivalent parallel capacitor of a piezoelectric resonator is realized to obtain a stable activation of oscillation and secure a large frequency variation. A crystal resonator is connected between an input and output terminals of an inverting amplifier to form a Colpitts-type oscillator circuit, an input terminal of another inverting amplifier is connected to the output terminal through a capacitor and the output terminal is connected to the input terminal through another capacitor to form a Miller capacitor circuit for electrically neutralizing a parallel capacitor existing equivalently between both sides of the crystal resonator.

Abstract: To provide a voltage controlled oscillator having a large variable width of oscillation frequency while ensuring oscillation starting performance, a P-channel MOS transistor Tr is made ON by detecting that an oscillation signal is provided with a predetermined amplitude value and oscillating operation is shifted from an initial state to a steady state by a detecting circuit OPC and a capacitor CA is connected in series with a series circuit constituted by a crystal resonator XL and a varicap diode CV. In the initial state, a load capacitance is reduced to thereby cancel an amount of reducing conductance gm of an oscillation amplifying portion to correspond to operation of the crystal resonator by a low amplitude and negative resistance necessary for maintaining excellent oscillation starting performance is provided and in the steady state, a width of changing the oscillation frequency is enlarged by enhancing an effect of the varicap diode CV.

Abstract: An oscillation control circuit is offered which can improve the startability of an oscillator circuit operating at high frequencies and at a low power-supply voltage. When the oscillation potential of the oscillation signal is between the inversion potential (1.2 volts) of a CMOS inverter IV1 and the inversion potential (1.8 volts) of a CMOS inverter IV2, the logical output value of a CMOS Schmitt inverter SI1 is 1. The output of a CMOS inverter formed by MOS transistors T32 and T33 is shorted out via a MOS transistor T34. Its logical output value is kept at 1. When the inversion potential of the CMOS inverter IV1 or the inversion potential of the CMOS inverter IV2 is exceeded, if the input voltage to the CMOS Schmitt trigger SI1 increases above its inversion potential (1.8 volts), the logical output value assumes a value of 0. The CMOS inverter formed by the MOS transistors T12 and T13 is first set into operation. The oscillation signal is inverted, setting a circuit LA at a later stage into operation.

Abstract: A fractional-N frequency synthesizer is offered which does not produce spurious signals of periodically conspicuous spectral intensities and can cancel produced spurious signals up to a practical level even with a spurious-canceling circuit of low accuracy. The synthesizer has a sigma-delta noise shaper. The integral and fractional parts of a frequency divide ratio-setting value that frequency-divides the output signal are set. The fractional part of the frequency divide ratio-setting value is applied to the sigma-delta noise shaper every phase comparison period. The output from the noise shaper and the integral part of the frequency divide ratio-setting value are summed up to thereby produce a sum. The output signal is frequency-divided, using this sum as a frequency divide ratio. The difference between the fractional part of the frequency divide ratio-setting value and the output from the sigma-delta noise shaper is produced and accumulated in an accumulator every phase comparison period.

Abstract: A highly efficient charge pump circuit featuring easy circuit design and formation as well as high reliability includes transistors M1-M4 individually having a diode connection configuration and interconnected in cascade, and is adapted to alternately apply a clock signal and an inverted clock signal to the transistors via capacitor elements C1-C4. The charge pump employs a depression-type transistor as the transistors M1-M4 and has an arrangement wherein the transistors M1, M2 on an input side have a greater gate length than the succeeding transistors M3, M4 for increasing the efficiency of boosting voltage. The charge pump circuit includes a single type of device so as to facilitate the circuit design and formation and also to enhance the reliability thereof.

Abstract: A current control circuit for maintaining constant current characteristics with respect to power source potential fluctuations has a first resistor with one end connected to a source potential first and second P-channel field effect transistors each having a source connected to the other end of the first resistor and a gate coupled to a gate of the other P-channel FET. The first P-channel FET has a drain directly connected to the mutually coupled gates. A second resistor connects a drain of the second P-channel FET to the mutually coupled gates, and a resistor element connects the mutually coupled gates to a zero potential. A voltage arising at the drain of the second P-channel FET is used as a gate-driving voltage for driving a gate of a current-setting transistor.

Abstract: In a delta sigma type D/A converter, in order to be capable of carrying out muting operation in steps at steps lower than 1 quantized step by digital processing, a multiplexor 2 for selectively outputting a mute code 15 for making an analog signal null and a thermometer code 14 to a local DAC4 is provided between a thermometer code converter 1 and the local DAC4, a time period of 1/M of a sampling period is made to constitute 1 cycle, at m1 (0≦m1≦M) cycle, the thermometer code 14 is made an output of the multiplexor 2 and at other m2 (m2=M−m1) cycle, the mute code 15 is made an output thereof and muting is carried out reducing the m1 cycle or muting is relieved by increasing thereof in steps at respective sampling period.

Abstract: Ferroelectric memory element having an MFIS structure including a silicon semiconductor substrate and an insulating film arranged above the silicon semiconductor substrate. The insulating film includes a low dielectric constant layer restraining film and a mutual diffusion preventive film so that an unnecessary, low dielectric constant layer is prevented from forming between the semiconductor substrate and the insulating film. A ferroelectric film is arranged on the insulating film. The low dielectric constant layer restraining film is thinner than the ferroelectric film.

Abstract: To restrain cycle-to-cycle jitter in a clock generator subjected to EMI a 2nd order PLL having a loop filter including a first capacitor and a first resistor, is provided where a reduction in a comparison frequency is avoided by using a clock modulating circuit. The clock modulation circuit is controlled by an intermediary signal provided by dividing an oscillation signal of a voltage controlled oscillator. The output of the clock modulation circuit is used to recurrently control a divider for dividing the output of the voltage controlled oscillator. Generation of high frequency noise is minimized by using a 1st order &Dgr;&Sgr; modulator(21) in the clock modulation circuit. The system behaves like a 3rd order PLL due to the presence of a second capacitor having a capacitance value of about {fraction (1/10)} or more than that of the first capacitor. The second capacitor is placed in parallel with the loop filter to restrain the cycle-to-cycle jitter by effectively removing the high frequency noise.

Abstract: An oscillator circuit adapted for a piezoelectric oscillator which has a weak oscillation output for generating high frequencies is provided. The speed of operation of the oscillator circuit is increased. An integrated circuit for such an oscillator circuit is also provided. The oscillator circuit has an amplifier portion consisting of CMOS inverters connected in cascade. MOS transistors forming the CMOS inverters have channel widths that decrease successively from the first stage to the last stage to improve the amplification factor of the amplifier portion at high frequencies. This makes it possible to amplify weak oscillation output from the quartz oscillator (XL). A filter circuit produces a peak of negative resistance at a frequency higher than conventional. This permit oscillation operation at higher frequencies.

Abstract: Automatic slice level control response to differential input signals is provided to remove in-phase noise and effects on S/N ratio Analog differential input signals Vinp and Vinn are inverted with respect to each other and applied to input terminals in1 and in2 of a comparator via resistors R1 and R2. A data stream is provided giving DSV=0. A charge pump is driven by a digital signal from the comparator. A transconductance amplifier produces output current Itrc1 and Itrc2 that are mutually differential signals and in proportion to the voltage difference between the output voltage Vcp from the charge pump and a reference voltage Vref. The output currents are supplied to the input terminals in1 and in2 of the comparator to provide a DSV=0.

Abstract: A temperature compensated oscillator has a frequency comparing circuit for comparing a frequency of an oscillating output signal of an oscillator circuit and a frequency of an external reference frequency signal externally inputted, and also has a sequential comparing register for determining each bit of a compensation datum based on this comparison. A digital signal from the sequential comparing register is applied to an input of a D/A converter for generating a control voltage of a varicap diode. The temperature compensated oscillator performs a self compensating operation for sequentially determining each bit of the sequential comparing register every frequency comparison, and conforming the frequency of the oscillating output signal to that of, the external reference frequency signal. The digital signal from the sequential comparing register is stored as compensating data corresponding to a detecting temperature of a temperature detector at that time.

Abstract: A drive circuit capable of adjusting a capacitive load operation, for example, respective brightness of an electroluminescence (EL) element. The drive circuit is a constant current drive system and causes a plurality of capacitive loads, for example, EL elements, to emit light. This is done by setting a coil drive signal applied to the gate of a transistor Tr1. The transistor generates a surge pulse by intermittently connecting a direct current power source to a coil L1 of a step-up circuit 1. The coil drive signal is set to a frequency in accordance with an EL element as a capacitive load driven alone or a combination of EL elements simultaneously driven. Power generated by the step-up circuit 1 can be selected, brightness of a driven EL element E1 or E2 can individually be set or brightness of the EL elements E1 and E2 simultaneously driven can be set.

Abstract: A pole-shifted noise shaper whose transfer function has a Z-plane in which the pole has been shifted out of the origin. The noise shaper suppresses idle pattern. The noise shaper has a dither adder (17) placed immediately before a quantizer (16) to add a dither signal to data about to be applied to the quantizer (16). This suppresses attenuation of the dither signal due to noise shaping. Therefore, the dither signal can be supplied effectively. The idle pattern appearing in the output signal can be suppressed. Since the pattern of the dither signal is varied at a frequency that is {fraction (1/16)} to ⅛ of the frequency of the operating clock signal, the frequency of noise component due to the dither signal lowers. The signal and the dither signal component can be easily separated in a rear stage.

Abstract: MOS semiconductor device including a substrate having source and drain regions laterally spaced from one another and a channel therebetween, a gate electrode over the channel and an oxide layer. The oxide layer includes a gate oxide layer between the gate electrode and the substrate, an oxide film having a having a thickness greater than a thickness of the gate oxide layer and a boundary oxide layer between the gate oxide layer and oxide film. The boundary oxide layer has a thickness between the thickness of the gate oxide layer and the thickness of the oxide film. The oxide film boundary oxide layer are formed by selective oxidation before formation of the gate electrode. The gate electrode has end portions extending over a portion of the oxide film while receiving no distortion from the boundary oxide layer to thereby improve breakdown voltage performance at the end portions of the gate electrode.

Abstract: To provide a cascode amplifying circuit having large amplifying gain without narrowing an output operational range or deteriorating response performance of the circuit even with a constitution by a small number of elements is achieved by applying negative feedback from the source to the gate of an MOS transistor M2 provided with an output terminal at the drain via the source and the drain of an MOS transistor M3 of N-channel type, the source and the drain of an MOS transistor M4 of P-channel type and a current mirror constituted by MOS transistors M5 and M6 of N-channel type. By this constitution, operation of the MOS transistor M3 is not effected with influence of lowering of voltage of the source of the MOS transistor M2, a wide output operational range is provided and mirror effect with respect to gate/drain capacitance of the MOS transistor is restrained to thereby restrain a reduction in response speed.

Abstract: To make compatible low consumption power formation of a control circuit of a light emitting element and high frequency formation of operational frequency band constituting a variety of usable combination elements of light emitting elements and light receiving elements, bias current is provided to a current mirror for dividing monitor current of a photodiode PD1 by a current source to thereby compensate drive function of a post stage in driving thereof by low current. Reference voltage of a current-voltage conversion portion is set in accordance with an input range of an operational amplifier of a gain adjusting portion at a post stage and input to the operational amplifier is fitted to an input range optimizing amplifying function. There are provided switching circuits SW1 and SW2 for selectively supplying monitor current from two photodiodes to respective APC loops of laser diodes LD1 and LD2 to thereby deal with a 2LD-1PD element and two of 1LD-1PD elements.

Abstract: In a sample-and-hold circuit using a completely differential type operational amplifier circuit, to promote operational stability, to restrain a variation in a balance point of a middle value of differential output signals and to promote stability and accuracy of an A/D converter are achieved by a constitution as bellow.

Abstract: To provide an amplifier excellent in temperature characteristic and providing an output signal having small crossover distortion in a wide power source voltage range, voltage values provided to positive phase input terminals of a second and a third amplifier 2 and 3 are made to correspond to voltages between sources and drains of a second P-channel MOS transistor Tr3 and a second N-channel MOS transistor Tr4, a first P-channel MOS transistor Tr1 and a first N-channel MOS transistor Tr2 constituting a power buffer 4, are driven by an output signal of a first operational amplifier 1 via the second and the third amplifiers 2 and 3 and therefore, there can be provided idling currents independently from power source voltage from low power source voltage, there can be provided an output signal having small crossover distortion in a wide power source voltage range and temperature dependency thereof can be improved.

Abstract: A differential comparison circuit capable of easily obtaining desired circuit accuracy and comparing differential signals with reduced influences of fluctuation of a power source voltage. Input/output terminals I/O1 and I/O2 of a latch circuit 1 are connected to the drain terminals of MOS transistors M1 and M2 having the same characteristics. Input terminals IN1 and IN2 are provided to the gate and source terminals of the MOS transistor M2, and input terminals IN3 and IN4 are provided to the gate and source terminals of the MOS transistor M2. A bias circuit 2 brings the MOS transistors M1 and M2 into the same bias state. The difference of the input signals supplied to the input terminals IN1 and IN2 is compared with the difference of the input signals supplied to the input terminals IN3 and IN4. Since the comparison result is outputted from the first and second input/output terminals I/O1 and I/O2, the input offset voltage does not affect the differential comparison circuit.