Abstract: To provide a resistor array circuit device and variable gain device which make possible precise setting of attenuation factors and the like as well as prevention of generation of gridge noise, a resistor array circuit device has resistors R1.sub.1 to R1.sub.n-1, each with a resistance value R, resistors R2.sub.1 to R2.sub.n, each with a resistance value aR, resistor R3 having a resistance value (l+b)R, switches SW.sub.1 to SW.sub.n for switching connection of resistors R2.sub.1 to R2.sub.n to a terminal T3 or a terminal T4, and a control circuit for controlling switches SW.sub.1 to SW.sub.n so that resistors R2.sub.1 to R2.sub.m-1 on a terminal T1 side of an arbitrary resistor R2.sub.m are connected to terminal T4 and resistors R2.sub.m to R2.sub.n on a terminal T2 side of resistor R2.sub.m are connected to terminal T3, the values of the a and b being determined based on b={-1+(1+4a).sup.1/2 }/2 and 1/2<a/(1+a+b).

Abstract: An integrated circuit device includes a first insulation layer formed on a substrate; a second insulation layer formed above the first insulation layer; a thin-film resistor formed on the second insulation layer; a third insulation layer in covering relation to the thin-film resistor and the second insulating layer; first contact holes penetrating the third insulation layer in association with the thin-film resistor; second contact holes penetrating through the second and third insulation layers; and conductive layers for electromagnetically shielding the thin-film resistor, the conductive layers including a first conductive layer formed between the first and second insulation layers below the thin-film resistor and a wiring layers formed above the thin-film resistor within the first and second contact holes.

Abstract: A sampling rate converter for converting a first signal having a first sampling rate to a second signal having a second sampling rate, includes a circuit for generating first data corresponding to the ratio of the second sampling rate to the first sampling rate. A second circuit generates second data by correcting the first data with corrective data. A third circuit generates third data corresponding to an estimated output timing of the second signal based upon the second data. A comparator compares the third data with a fourth data corresponding to the actual output timing of the second signal to generate comparative data. A corrective circuit is responsive to the comparative data to generate the corrective data. A further circuit is responsive to the first and third data for generating the second signal.

Abstract: A semiconductor device has a DRAM portion forming a cache memory and a flash memory portion fabricated on a common substrate, fabricated by a process based on the process of fabricating the flash memory portion. An electrode layer common to capacitors of the DRAM portion and a floating gate layer of the flash memory portion are formed simultaneously from the same material. An electrode layer of the upper capacitor of the DRAM portion, a gate electrode layer for a transistor of the DRAM portion, and a control gate layer of the flash memory portion are formed simultaneously from the same material.

Abstract: A sampling rate converter includes an arithmetic circuit for performing digital filtering processing for sampling rate conversion, and a circuit for calculating a sampling rate ratio. A memory circuit stores a plurality of groups of filter coefficients which are used in the digital filtering processing performed in the arithmetic circuit, corresponding to a plurality of sampling rate ratio ranges. A select circuit selects a filter coefficient group corresponding to the sampling rate ratio. The select circuit is arranged such that even if the sampling rate ratio is outside a sampling rate ratio range corresponding to a filter coefficient group selected at the present time, the select circuit continues to select the filter coefficient group selected at this time as long as the sampling rate ratio is within a predetermined range outside the sampling rate ratio range.

Abstract: A method of making a semiconductor device having formed thereon an inductor comprises a silicon substrate. A cut out region is obtained by removing a part of the silicon substrate in a hollow shape which may be a hollow cavity or a hollow cavity with an insulating material having a low complex permittivity such as silicon oxide buried therein. An insulator layer is formed on the cut out region and on the periphery thereof. A connection layer serves as one of the leads of the inductor and is formed using an electric conductive material such as a metal or doped polycrystalline silicon. A contact hole is provided in the interlayer insulation layer. A connection layer serves as an inductor and the other lead of the inductor, which is formed using an electric conductive material such as a metal. A protective insulator layer is also provided on the top of the structure.