Abstract: A digital data processing circuit has an inverting circuit for inverting a positive/negative sign of the output data of an encoding circuit. A correcting circuit returns the inverted sign of the data to an original sign of data after decoding. Offset is made for truncation noises caused by the respective filtering operations in the encoding circuit and said decoding circuit. Sound quality is suppressed from degrading without increasing the circuit scale.

Abstract: There is disclosed an oscillator circuit comprising the first load capacitor with one electrode there of being connected with an input side of a CMOS inverter within a quartz oscillator circuit, and the second load capacitor with one electrode there of being connected with the output side of the inverter, wherein the inverter is coupled to a lower potential side via a current-limiting device, and the other electrodes of the first and second load capacitors are coupled to a lower potential side via the above-described current-limiting device. Thus, variations in the power-supply voltages synchronized with oscillation are reduced with realization of lower current consumption.

Abstract: An oscillation circuit that improves the duty controllability by cross-coupling ring oscillators that are comprised of current inverters. The sources of current supply circuits 4a-4c and 6a-6c are connected to a power supply and their drains are connected to terminals A in corresponding current inverters, respectively. Each of the gates of those current supply circuits receives an output of a current inverter corresponding, one to one, to a current inverter to which the current supply circuit is connected.

Abstract: To provide a semiconductor device and a method of making a semiconductor device capable of preventing exfoliation at a pad electrode portion, a barrier metal layer 14, a silicon layer 15 and an aluminum layer 16 are formed on a side of a main face of a silicon substrate 11 (step A), the barrier metal layer 14, the silicon layer 15 and the aluminum layer 16 are patterned into a shape of a pad electrode (step B) and a silicide layer 17 is formed by an annealing treatment successive to the patterning step (step C).

Abstract: A CMOS circuit prevents feedthrough current and has a small-scaled circuit constitution. An output stage has a P-channel MOS transistor and an N-channel MOS transistor with drains connected to each other to form an output terminal and gates respectively connected to output terminals of first and second series circuits. The first and second series circuits control supply of power and each includes an N-channel MOS transistor and a P-channel MOS transistor with drains connected together to form the output terminal and gates connected together to form an input terminal. A delay circuit receives an input signal and produces a delayed input signal which drives the input terminals of the first and second series circuits. P-channel and N-channel MOS transistors control power potentials applied to sources of the respective P-channel and N-channel MOS transistors of the second and first series circuits and are driven by the input signal which is applied to their gates.

Abstract: A phase-locked loop (PLL) circuit capable of attaining high-speed frequency transition with enhanced reliability. To this end, outputs of a reference signal source (1) and voltage-controlled oscillator (VCO) circuit (3) are frequency-divided by frequency divider circuits (2, 4), respectively. A phase comparator circuit (5) is provided for outputting an error signal indicative of a phase difference between these signals, if any. A window generator circuit (9) is connected for outputting a window signal; where the error signal does not fall within the range of a pulse width of this window signal, a level generator circuit generates a boost voltage having its potential near the control voltage value of the VCO (3) for use in generating of a target frequency.

Abstract: An IC testing apparatus has a detecting circuit for detecting an inversion of an output state of a test output from an IC under test in response to application of a clock signal, a comparing circuit for comparing a value preset in a storage circuit with the output state of the test output and an output state of the detecting circuit. In a first comparison operation, the number of pulses of the clock signal applied to the IC under test is less than the number of pulses required to invert the output state of the test output by one pulse and the test output and detector output are compared with corresponding values preset in the storage circuit at times coincident with a test strobe signal synchronized with the clock signal. In a second comparison operation, another clock pulse is applied to the IC under test to make the total number of pulses equal to that needed for inverting the test output and the above comparisons are again made with corresponding preset values.

Abstract: A digital audio recorder and system efficiently increases a sampling frequency and a number of bits of a digital audio recording. The digital audio system has a frequency analyzer receives a first digital waveform data having a sampling frequency fs1 and N1 number of bits and determining a sampling frequency fs2 in accordance with a highest frequency component of the first digital waveform data. A delay device delays the first digital waveform data a time period equal to the time required for the frequency analyzer to determine the highest frequency component and then sends the first digitial waveform data to a frequency converter. The frequency converter converts the first digital waveform data to a second digital waveform data having the sampling frequency fs2 and a number of bits N2.

Abstract: A phase comparator has a first comparing circuit and a second comparing circuit. The first comparing circuit produces a first output pulse having a duration equal to a phase lead of a first input signal with respect to a phase of a second input signal. The first phase comparator also produces a second output pulse equal in duration to a phase lag of the first input signal with respect to the phase of the second input signal. The second comparing circuit produces a third pulse equal in duration to a phase lead of a third input signal with respect to a phase of a fourth input signal. The second comparator also produces a fourth output pulse equal in duration to a phase lag of the third input signal with respect to the phase of the fourth input signal.

Abstract: A semiconductor memory cell device exhibiting superior cell reliability comprising a dual layer floating gate wherein the thin upper layer of the floating gate overlaps the edges of surrounding field insulating regions and has rounded edges to minimize leakage concerns. The tunnel dielectric separating the dual layer floating gate from the substrate comprises a layer of uniform thickness which is grown prior to the formation of the field insulating regions. The Fowler-Nordheim tunneling mechanism is used for programming and erasing the inventive cells in a programming process flow which comprises flash programming all cells on a word line, sensing current on a selected cell, and selectively erasing the charge on the cell by applying a higher voltage on the intersecting bit line than is applied to the word line, until the sensed current is as desired.

Abstract: A transferred data recovery apparatus capable of recovering transferred data from a transferred data signal has a first comparator for comparing transferred data signal with a reference level R to output binary-quantized data signal representing whether or not the transferred data signal is higher than the reference level R. A sample and hold circuit is driven by a clock signal and samples the binary quantized data signal each clock period to output sampled digital data to an averaging circuit. The averaging circuit sequentially averages a predetermined number of the sampled digital data each clock period to produced averaged outputs. A second comparing circuit digitally compares the averaged outputs against an upper reference level and a lower reference level dependent upon the direction of change to produce a recovered data output. The recovered data output goes low when the averaged output goes lower than the lower reference level and goes high when the averaged output goes above the upper reference level.

Abstract: In an APC system waveform dam compression apparatus which generates an optimum prediction coefficient utilizing a block calculation process in a first mode and generating prediction data utilizing a block calculation process based on this optimum prediction coefficient in a second mode with respect to a fixed number of blocked waveform data, to make possible use of suitable data in the first prediction calculation process of each block calculation process. A data holding section for holding data corresponding to at least final first waveform data to be used in a final prediction calculation process of a block calculation process in a second mode, and a first selection section for using data held in the data holding section in place of data memorized in a second delay section in each first prediction calculation process of each block calculation process of the next block are provided in an operating circuit.

Abstract: To provide a method of forming a resist pattern in a readily controllable manner and at low costs, in a first exposure step, a resist layer is subject to exposure through a mask. In the next, first developing step, a stepped portion 4 is formed in the resist layer. In a second exposure step, the resist layer is again subject to exposure. At this time, phase shift by 180.degree. occurs in the stepped portion so as to allow some area of the resist layer along the step to be not subject to exposure. In the second developing step, the exposed area of the resist layer 2 is removed to form a resist pattern along the step. Accordingly, the present invention is less subject to diffraction than the case where a phase shifter is employed, and is able to form a resist pattern in a readily controllable manner and reduce fabrication costs.

Abstract: To minimize error in size and form a thick oxide layer as field insulating means in a narrow isolation region, a method of fabricating a semiconductor device is carried out as followings.A polysilicon layer 3 is formed on a silicon substrate 1. A silicon nitride layer 5 is then formed on the polysilicon layer 3. Thereafter, an aperture 7 is formed in the silicon nitride layer 5 and reaches the polysilicon layer. A silicon layer 9 is formed in the aperture 7 by epitaxial growth technique. The silicon layer 9 is selectively oxidized to form an oxide layer 10 as field insulating means. The silicon nitride layer 5 and a portion of the polysilicon layer 3 which was left unoxidized are removed. This makes it possible to form the desired thick oxide layer as field insulating means in a narrow region.

Abstract: A writing circuit for non-volatile memory capable of preventing the structure of the circuit from becoming complicated in an integrated circuit from the points of view of logic and layout by reducing the number of kinds of control signal voltages. The circuit includes a first NMOS transistor N1, a first PMOS transistor P1, a second NMOS transistor N2 which serves as a non-volatile memory write terminal and a depression type MOS transistor D1 having a source to which a control signal PGM for controlling the output condition of the above-mentioned write terminal is applied.

Abstract: In a waveform data reproducing apparatus for a digital audio system, deterioration of sound quality is prevented by a digital audio waveform data reproducing apparatus which includes a digital preemphasis circuit 12 for digitally preemphasis-processing digital audio waveform data a1 to produce digitally preemphasized data c1, a D/A converter 14 for D/A-converting either the waveform data a1, or the digitally preemphasized data c1, a switch circuit 13 for causing the waveform data a1 to be connected to the D/A converter 14 when the waveform data a1 has been emphasis-processed, and for causing the digitally preemphasized waveform data c1 to be connected to the D/A converter 14 when the waveform data a1 is not emphasis-processed, and an analog deemphasis circuit 14 for analogically deemphasis-processing the output signal from the D/A converter 14.

Abstract: There is disclosed a voltage-controlled oscillator circuit capable of being operated at low power supply voltages and accomplishing low electric power consumption. The circuit permits the duty cycle to be controlled well. The circuit is capable of operating at high speeds. The circuit comprises a first and a second dynamic latch circuits producing oscillation output. Each dynamic latch circuit consists of a series combination of a P-channel MOS transistor and an N-channel MOS transistor. An output terminal is connected to the junction of these two transistors. The output from each latch circuit is inverted according to the voltage at the gate of each MOS transistor and dynamically latches the state of the output. This inversion is performed by turning on the MOS transistors by first and second capacitive elements and by first and second comparator circuits. The capacitive elements are charged and discharged by the outputs from the dynamic latch circuits.

Abstract: A method of accurately recording and reproducing an analog signal having a wide dynamic range with a small amount of information first samples amplitude values of an analog waveform which are then converted to a digital signal. Plural frames of data are stored in a buffer circuit. For each frame, the differences between successive values of the digital signal are extracted to form a second digital signal having an amount of shift S common to one frame, which is established and stored in a memory. In response to the amount of shift, the second digital signal is shifted toward lower bits thereof to compress the second digital signal into a third digital signal having less bits which is stored. When the difference values are small, the amount of shift is reduced to suppress errors produced during compression. When the difference values are large dynamic range is obtained, thereby coping with great signal variations without neglecting small variations in the analog signal.

Abstract: A downflow spin dryer, includes a housing; a rotor rotating within the housing in a direction of rotation, the rotor including first and second opposite mounting holes at different heights; a cradle fitted within the rotor for accommodating semiconductor substrates to be dried, the cradle having a rear portion and a front portion as viewed with respect to the direction of rotation of the rotor, the cradle being fitted to the rotor such that the rear portion of the cradle is at a lower position than the front portion of the cradle, the cradle including first and second opposite mounting holes in alignment with the first and second mounting holes, respectively, of the rotor when the cradle is fitted within the rotor, the first and second mounting holes of the cradle being at the same height; screws for entering the first mounting holes of the cradle and the rotor, and for entering the second mounting holes of the cradle and the rotor, so as to mount the cradle within the rotor; an air inlet in an upper surface

Abstract: A serial-to-parallel type multiplier capable of performing a highspeed calculation with high precision includes a selection circuit provided in a unit calculation block, an output of this selection circuit being input into an adder, and the selection circuit selectively outputs either a logic product between a multiplier bit to be input into this unit calculation block and a multiplicand bit input into this unit calculation block within one unit time period or a logic product between a multiplier bit to be input into this unit calculation block and a multiplicand bit input into this unit calculation block within a unit time period prior to the above-described one unit time period.