Abstract: An electronic device includes a controller, a clock generator, a first operation interface and a first functional unit. The controller generates a first clock enable signal, and then generates a first operation instruction. The clock generator generates a first clock according to the first clock enable signal. The first operation interface generates a first power supply signal according to the first clock, and translates the first operation instruction into a first operation signal. The first functional unit is enabled according to the first power supply signal, and starts to operate according to the first operation signal.

Abstract: A white light emitting device includes: first light-emitting units to which a first current is applied; and second light-emitting units to which a second current which is different from the first current is applied. When the first current is applied to the first light-emitting units and the second current is applied to the second light-emitting units, an average emission chromaticity of the first light-emitting units and an average emission chromaticity of the second light-emitting units are identical colors. When the same current is applied to both the first light-emitting units and the second light-emitting units, the average emission chromaticity of the first light-emitting units and the average emission chromaticity of the second light-emitting units are non-identical colors.

Abstract: A method of speeding up a secure boot process and an electronic device using the method. The method includes the following. Whether a storage medium stores a pre-stored hash value corresponding to an image file for the secure boot process is determined. A hash value of the image file is calculated to determine whether the hash value matches the pre-stored hash value in response to the storage medium storing the pre-stored hash value. Firmware in the image file is executed to boot up the electronic device in response to the hash value matching the pre-stored hash value.

Abstract: A monitoring system includes an arithmetic processor. The arithmetic processor receives captured image information representing a captured image obtained by capturing an image of a subject and generates notification information representing a particular notification content depending on a condition of the subject. The arithmetic processor includes a first arithmetic processor and a second arithmetic processor. The first arithmetic processor obtains a condition quantity by quantifying the condition of the subject by reference to the captured image information and based on a parameter about a human activity status. The second arithmetic processor selects, according to the condition quantity, the particular notification content from contents of notification classified into N stages, where N is an integer equal to or greater than three.

Abstract: A controller used in a computing device executes the following steps. When a security profile stored in a storage device is successfully verified, according to a security profile configuration stored in the controller, an operation mode described in the security profile is used. When the used operation mode is in a non-secure mode, the booting of the computer device is directly completed. When the used operation mode is a secure mode and a main BIOS of the computing device is not valid, at least one BIOS stored in the storage device is used to recover the main BIOS, and the computer device is rebooted. When the used operation mode is a secure mode and the main BIOS is valid, but the storage device does not store the main BIOS, the main BIOS is backed up and to be stored in the storage device.

Abstract: A bus system is provided. A plurality of slave devices are electrically connected to a master device through an enhanced serial peripheral interface (eSPI) bus. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. In a first phase of a plurality of phases in each assignment period of an assignment stage after a synchronization stage, the first slave device is configured to control the alert handshake control line to a second voltage level via the alert handshake pin. In the phases of each of the assignment periods except for the first phase, a first slave device of the slave devices is configured to control the alert handshake control line to communicate with the slave devices via the alert handshake pin. The first phase corresponds to a first slave device.

Abstract: A distance information acquisition device includes: a light emitter which emits light according to an emission pulse indicating emission; a solid-state imaging element which performs exposure according to an exposure pulse indicating exposure; an emission/exposure controller which generates a timing signal indicating a plurality of pairs of the emission pulse and the exposure pulse having a time difference that is different in each of the plurality of pairs; and a multipath detector which obtains a sequence of received light signals from the solid-state imaging element by the emission and the exposure that correspond to each of the plurality of pairs, compares the obtained sequence of received light signals and reference data created in advance as a model of a sequence of received light signals in a multipath-free environment, and determines the presence or absence of multipath according to a difference in a comparison result.

Abstract: A face-down mountable chip-size package semiconductor device includes a semiconductor layer and N (N is an integer greater than or equal to three) vertical MOS transistors in the semiconductor layer. Each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor. The semiconductor layer includes a semiconductor substrate. The semiconductor substrate functions as a common drain region for the N vertical MOS transistors. For each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor.

Abstract: A variable resistance non-volatile memory element includes first and second electrodes and a variable resistance layer between the electrodes. The layer has a resistance value reversibly variable based on an electrical signal. The layer includes a first variable resistance layer that includes an oxygen deficient first metal oxide containing a first metal element and oxygen, and a second variable resistance layer that includes a composite oxide containing the first metal element, a second metal element different from the first metal element, and oxygen, and having a different degree of oxygen deficiency from the first metal oxide. The composite oxide has a lower degree of oxygen deficiency than the first metal oxide. At room temperature, the composite oxide has a smaller oxygen diffusion coefficient than a second metal oxide containing the first metal element and oxygen, and having the degree of oxygen deficiency equal to that of the composite oxide.

Abstract: A semiconductor circuit includes: an analog circuit that inputs a measured signal; and a digital circuit that outputs a digital output signal. The analog circuit includes: a correction element group including one or more correction elements each for correcting an offset that is an amount of shift caused by a variation in characteristics of the analog circuit to occur in a path for transmitting the measured signal; and a test element group including one or more test elements for testing the one or more correction elements. The digital circuit tests the correction element group using the test element group.

Abstract: A semiconductor device includes a metal-insulator-semiconductor high-electron-mobility transistor (MISHEMT) and a Schottky gate HEMT. The Schottky gate HEMT and the MISHEMT are connected in series, and a Schottky gate of the Schottky gate HEMT is electrically connected with the source of the MISHEMT so as to generate a forward diode from the source to the drain of the MISHEMT. The series-connected structure is good for increasing the breakdown voltage of the semiconductor device, and the forward diode can reduce the power loss.

Abstract: A bus system is provided. A plurality of slave devices are electrically connected to a master device through an enhanced serial peripheral interface (eSPI) bus. The slave devices are electrically connected together via a control line. A first slave device is configured to provide a first clock signal to each second slave device via the control line, so that a second clock signal of each second slave device is synchronized with the first clock signal. After the second clock signals are synchronized with the first clock signal, each second slave device is configured to adjust a phase of the second clock signal in a clock phase shift stage, so that each second clock signal has a phase difference with the first clock signal. The phase differences between the second clock signals of the second slave devices and the first clock signal are different.

Abstract: A semiconductor device includes: a channel layer not containing Al; a barrier layer above the channel layer containing Al; a recess; and an ohmic electrode in the recess, which is in ohmic contact with a two-dimensional electron gas layer. An Al composition ratio distribution of the barrier layer has a maximum point at a first position. The semiconductor device includes: a first inclined surface of the barrier layer which includes the first position and is in contact with the ohmic electrode; and a second inclined surface of the barrier layer which intersects the first inclined surface on a lower side of the first inclined surface, and is in contact with the ohmic electrode. To the surface of the substrate, an angle of the second inclined surface is smaller than an angle of the first inclined surface. A position of the first intersection line is lower than the first position.

Abstract: A power converter is provided. The power converter includes a switched-capacitor conversion circuit and an inductor buck circuit. The switched-capacitor conversion circuit receives an input voltage at an input terminal and performs a switching operation to convert the input voltage to an intermediate voltage. The inductor buck circuit is coupled to an output terminal of the switched-capacitor conversion circuit to receive the intermediate voltage and operates at a constant on-time to generate an output voltage at a conversion output terminal according to the intermediate voltage. The inductor buck circuit includes an inductor. In response to that a state of an inductor current used for charging the inductor corresponds to a predetermined condition, a switching action of the switching operation is enabled, so that the switched-capacitor conversion circuit is switched from a first turned-on state to a second turned-on state.

Abstract: Methods and systems provide for modulating light sources in panel displays of devices, such as light emitting diodes (LEDs), to provide indications as to device performance. The modulations are at low and high frequencies. The low frequencies provide visible blinking patterns, indicative of an event in the device, and the high frequencies, provide non-visible blinking patterns, indicative of one or more parameters associated with the event.

Abstract: A management controller is coupled to a plurality of external devices. The management controller includes a control circuit and a transmission circuit. The control circuit generates a control signal according to a first counting value and a second counting value. The transmission circuit is coupled to the external devices. In response to the first counting value not being equal to a first target value, the transmission circuit enters a circulating mode according to the control signal. In the circulating mode, the transmission circuit triggers the external devices in order. In response to the second counting value not being equal to a second target value, the transmission circuit continues to operate in the circulating mode. In response to the second counting value being equal to the second target value, the transmission circuit exits the circulating mode.

Abstract: A continuous memory access acceleration circuit, an address shift circuit, and an address generation method are provided. An arithmetic circuit calculates a memory access address according to temporary data provided by a register circuit. A counter provides a count value. A counting control circuit controls the counter to accumulate the count value according to access times of a memory. An adder circuit adds the memory access address and the count value to generate a target memory access address.

Abstract: Provided is a clock switching device including a first latch circuit, a second latch circuit, and a switching circuit. The first latch circuit latches a first selection signal based on triggering of a first clock signal. The second latch circuit latches a second selection signal based on triggering of a second clock signal. A reset terminal of the second latch circuit is coupled to the first latch circuit. The second latch circuit is selectively reset based on an output of the first latch circuit. The switching circuit is coupled to an output terminal of the first latch circuit and an output terminal of the second latch circuit. The switching circuit selects one of the clock signals as an output clock signal of the clock switching device based on the selection signals.

Abstract: Provided are a thermal sensor and a manufacturing method thereof. The thermal sensor includes a transistor and a thermal sensing device. The thermal sensing device is disposed in a recess in a substrate and electrically connected to the transistor. The thermal sensing device includes a first dielectric layer, a metal silicide reflective layer, a second dielectric layer, and a thermal absorbing layer. The first dielectric layer is disposed on sidewalls and a bottom of the recess. The metal silicide reflective layer is disposed on the first dielectric layer located on the bottom of the recess. The second dielectric layer is disposed at a top of the recess. The thermal absorbing layer is disposed on the second dielectric layer.

Abstract: A parameter checking method includes substituting a plurality of initial parameters into a data integrity algorithm to obtain syndrome data using a processor, and using a hardware cipher to calculate a calculation result based on the data integrity algorithm based on a plurality of calculation parameters corresponding to the initial parameters. Moreover, when the processor determines that the syndrome data is not the same as the calculation result, the processor outputs a hacker attack message, indicating that at least one of the calculation parameters has been tampered with.