Abstract: A semiconductor laser element that includes a semiconductor layer including a waveguide formed in an intra-layer direction of the semiconductor layer and a window region formed in a front-side end face of the waveguide, has a current-laser optical output characteristic in which, at an operating temperature of 25° C.±3° C., a laser optical output has a maximum value at a first driving current value and the laser optical output is at most 20% of the maximum value at a second driving current value greater than the first driving current value, and is not damaged at the second driving current value.

Abstract: A battery control system is provided with battery monitoring control circuits for measuring an output voltage of an individual or secondary battery cells, which are connected in an assembled battery divided into blocks; and a control circuit for controlling the battery monitoring control circuits. Each of the batter monitoring control circuits includes a communication interface for communications between the battery monitoring control circuits or communications with the control circuit; a power converter for converting a start-up signal into a DC voltage; and a start-up circuit that receives the DC voltage and generates a start-up control signal for starting the battery monitoring control circuit.

Abstract: A power supply device for providing a driving voltage of an encryption/decryption device. When the encryption/decryption device is in operation and its driving voltage falls within the voltage range formed by an upper limit voltage and a lower limit voltage, only a supply voltage provided by a secure power supply device is used as the driving voltage for the encryption/decryption device. When the encryption and decryption device is in operation and its driving voltage falls outside the voltage range formed by the upper limit voltage and the lower limit voltage, the supply voltage and a stable voltage provided by the stable voltage source are used as the driving voltage at the same time, the supply voltage is further adjusted until the driving voltage falls within the voltage range formed by the upper limit voltage and the lower limit voltage, and then continue to use only the supply voltage as the driving voltage.

Abstract: An UART interface circuit is provided in the invention. The UART interface circuit is configured in an electronic device. The UART interface circuit includes a baud-rate generating circuit, a control circuit, and a receiving circuit. The baud-rate generating circuit is configured to generate a baud rate and a start-bit cycle. The control circuit obtains the wakeup stable time from the wakeup time circuit of the electronic device and obtains the start-bit cycle from the baud-rate generating circuit. The receiving circuit is configured to capture data from the start bit or the first data bit of UART data. When the electronic device is woken up by the UART data, the control circuit compares the start-bit cycle with the wakeup stable time to direct the receiving circuit to start capturing data from the start bit or the first data bit of the UART data.

Abstract: An imaging apparatus includes a light emitter, a pixel section, and a signal processor which calculates distance information of a subject. The pixel section includes a photoelectric converter, first and second read-out gates, and a plurality of charge accumulators including a first charge accumulator and a second charge accumulator. The first read-out gate is activated in a first period and deactivated in a second period. The second read-out gate is activated in the first period and the second period. The signal processor calculates the distance information based on a total amount of signal charges accumulated in the charge accumulators in the first period and the second period and a difference between an amount of signal charges accumulated in the second charge accumulator in the first period and the second period and an amount of the signal charge accumulated in the first charge accumulator in the first period.

Abstract: A clock filter device for finding an optimal cut-off frequency of a clock filter through a controller to achieve an effective clock filtering is illustrated. Further, in the calibration mode, a reference clock that has not passed the clock filter and a reference clock that has passed the clock filter make a first counter and a second counter count respectively. After the first counter counts to a specific value, a count value of the second counter is obtained. The count values of the first counter and the second counter are compared to each other to determine whether the two values are approximate or not. When the two values are not approximate, the previous cut-off frequency of the clock filter is taken as the optimal cut-off frequency. Therefore, the clock filter can adopt the optimal cut-off frequency in a working mode to effectively filter out the noise an input clock.

Abstract: A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 ?m; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 ?m. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-?m square region located at least 13 ?m inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.

Abstract: A solid-state imaging device includes: pixels disposed in a matrix of pixel rows and pixel columns; control wires provided for the pixel rows or the pixel columns, and each connected to at least two pixels out of the pixels, the at least two pixels being included in one of the pixel rows or the pixel columns for which the control wire is provided; drive circuits that are provided for the control wires, each include buffer elements in at least two stages, and each output a control signal to one of the control wires for which the drive circuit is provided, the buffer elements in the at least two stages being connected in series; and a first wire that short-circuits output wires of the buffer elements in one of the at least two stages in at least two of the plurality of drive circuits.

Abstract: An electronic circuit includes a driving cell, one or more driven cells and one or more inverters. The driving cell has two or more inputs and at least one output and is configured to toggle the output between first and second logic states in response to the inputs. Each driven cell has two or more inputs, of which at least one input is configured to be driven by the output of the driving cell. The one or more inverters are placed in a signal network that connects the driving cell to the driven cells. The inverters are configured to balance, over the signal network, (i) a first capacitive load charged by electrical currents caused by transitions from the first logic state to the second logic state and (ii) a second capacitive load charged by electrical currents caused by transitions from the second logic state to the first logic state.

Abstract: A gas monitoring system includes at least one sensor device that detects gas and outputs a detection result; and a gateway that receives the detection result. The at least one sensor device includes a sensor module having a gas sensor that detects gas; an analog-to-digital (A/D) converter that processes the detection result outputted from the gas sensor; a communication module that communicates with the sensor module and transmits information processed by the A/D converter exteriorly of the at least one sensor device; a power source that is an electric power source of the sensor module; and a power source that is an electric power source of the communication module.

Abstract: An electronic device is provided. The electronic device includes a power pin, a main circuit, and a start-up circuit. The power pin is configured to receive a power supply. The start-up circuit includes a switch coupled between the power pin and the main circuit, a timer and an oscillator. The switch is configured to selectively provide the power supply to the main circuit in response to a control signal. The oscillator, is configured to provide a periodic signal. The timer is configured to provide the control signal to turn on the switch when counting to a start-up time according to the periodic signal, so that the main circuit is configured to provide a fixed voltage according to the power supply.

Abstract: A clock monitor circuit includes a monitor and a tunable counter. The monitor can monitor a clock under test. The tunable counter can count an integer according to a reference clock and set a target number. If a stable signal relative to the clock under test is toggled, the tunable counter can switch the target number from a large number to a small number. The tunable counter can perform an automatic detection process, so as to transmit a check signal to the monitor. In response to the check signal, if the clock under test is undetectable, the monitor will not transmit any confirmation signal back to the tunable counter, and the tunable counter will gradually increase the integer. When the integer is equal to the target number, the tunable counter generates a failure signal.

Abstract: A light-emitting device including: a mounting substrate including a mounting surface; a light-emitting element disposed on the mounting surface; a light transmissive component disposed on the light-emitting element; and a resin component directly contacting and covering a side surface of the light-emitting element and a side surface of the light transmissive component. The resin component includes a peripheral portion that directly contacts and covers the side surface of the light transmissive component, a protrusion that protrudes from the peripheral portion, and a cover portion that directly contacts and covers an outer edge portion of a topmost surface of the light transmissive component. The height from the mounting surface to a top of the cover portion is greater than a height from the mounting surface to the topmost surface of the light transmissive component, and the topmost surface of the light transmissive component includes a region exposed from the resin component.

Abstract: A control circuit including a timer circuit and a voltage monitor circuit is provided. The timer circuit enables a trigger signal every a fixed time interval in response to a wake-up event. The voltage monitor circuit is configured to determine whether the operation voltage reaches the expected voltage and includes a signal-generating circuit, a first delay circuit, a second delay circuit, and a determination circuit. The signal-generating circuit generates a reference signal according to the trigger signal. The first delay circuit receives the operation voltage and delays the reference signal to generate a first delay signal. The second delay circuit delays the trigger signal to generate a second delay signal. The determination circuit enables a wake-up signal according to the reference signal, the first delay signal, and the second delay signal in response to the wake-up event.

Abstract: An apparatus for protecting a processor includes an input interface and protection circuitry. The input interface is configured to monitor code instructions that are processed by the processor, one or more of which code instructions including one or more error-detection bits. The protection circuitry is configured to detect an error in the program code using the error-detection bits, and to initiate a responsive action in response to detecting the error.

Abstract: A power consumption evaluation device and a power consumption evaluation method are provided. The power consumption evaluation device includes a power converter, a counter, and a controller. The power converter includes a power switch. The power switch performs a switching operation according to a control signal, so that the power converter supplies power to a corresponding load among at least one load. The counter counts one of a positive pulse and a negative pulse of the control signal during a measurement period to obtain a count value. The controller generates an evaluation result of the corresponding load according to the count value.

Abstract: A reference current/voltage generator includes a current mirror unit and a current-mode temperature compensation unit. The current mirror unit generates a first current, a first sum current and a second sum current flowing through first to third terminals thereof, and the first current, the first sum current and the second sum current are in a multiple relationship. The current-mode temperature compensation unit is electrically connected to the second and third terminals of the current mirror unit, and when a voltage on the second terminal is equal to a voltage on the third terminal, the first sum current is a sum of a current proportional to absolute temperature (PTAT) and a current complementary to absolute temperature (CTAT). The first terminal of the current mirror unit is an output terminal of the reference current/voltage generator and configured to output the first current as a reference current.

Abstract: A distance-measuring imaging device includes a light source that applies light according to timing of a light emission signal; a solid-state imager that performs, for an object, exposure according to timing of an exposure signal, and generates raw data corresponding to an exposure amount of the exposure; a signal amount comparator that determines a magnitude relationship in signal amount in the raw data; and a distance calculator that generates and outputs a distance signal based on a determination result. The solid-state imager accumulates, in each of different signal accumulation regions for accumulating signals detected in a same pixel, a signal by exposure in an exposure period that differs in exposure signal timing. The signal amount comparator determines the magnitude relationship between the signals accumulated in the signal accumulation regions. The distance calculator calculates the distance to the object using an arithmetic expression selected depending on the determination result.

Abstract: A semiconductor device includes: a semiconductor layer in a rectangular shape in a plan view; a transistor provided in a first region; and a drain lead-out region provided in a second region. A border line is a straight line parallel to longer sides of the semiconductor layer. The first region includes a plurality of source pads and gate pads. The second region includes a plurality of drain pads. One gate pad among the gate pads is disposed to dispose none of the plurality of source pads between (i) the one gate pad and (ii) one longer side and one shorter side. One drain pad among the plurality of drain pads is in the same shape as the one gate pad and is disposed close to a second vertex. The plurality of source pads include a source pad that is in a rectangular shape or an obround shape having a longitudinal direction parallel to the longer sides of the semiconductor layer.

Abstract: A control circuit and method for detecting a glitch signal on a bus are provided. The control circuit includes: input ends, respectively receiving a data signal and a clock signal from the bus; a counter, for calculating a time or a number of times in a low level period of the clock signal; a comparator, receiving an output of the time counted by the counter and a threshold value, and generating a comparison result by comparing the time and the threshold value; and an error detector, coupled to the comparator to receive the comparison result, and generating an error flag. When the comparison result indicates that there is a level change during the low level period of the clock signal, the error detector generates an error flag.