Abstract: A power verification circuit is provided. The power verification circuit includes a current source, a resistive random access memory (RRAM) cell and a Zener diode. The current source is coupled to a power terminal. The RRAM cell is coupled between the current source and a ground terminal. The Zener diode has an anode coupled to the RRAM cell and a cathode coupled to the power terminal. The impedance of the RRAM cell is determined by the power voltage applied to the power terminal.

Abstract: An event detection controller for a circuit system controlled by a pulse wave modulation signal, can perform a specific event handling when a specific event is detected, wherein the specific event handling includes stopping a pulse wave modulation device, starting up the stopped pulse wave modulation device, controlling the pulse wave modulation device to change the pulse wave modulation signal, outputting a wake-up signal to wake up the circuit system, controlling the pulse detector to change its detection configuration, changing a cumulative occurrences number of the specific pattern of an event discrimination module, outputting a control signal or a first data signal to a peripheral device through a bus connected to an event response module and/or requesting the peripheral device to send a second data signal through the bus.

Abstract: A true random-number generator generating a random variable is provided. A first delay circuit delays an input signal to generate a first delayed signal. A second delay circuit delays the first delayed signal to generate a second delayed signal. A first sampling circuit samples the input signal according to a clock signal to generate a first sampled signal. A second sampling circuit samples the first delayed signal according to the clock signal to generate a second sampled signal. A third sampling circuit samples the second delayed signal according to the clock signal to generate a third sampled signal. An operational circuit generates the random variable and adjusts a count value according to the first sampled signal, the second sampled signal, and the third sampled signal. The operational circuit adjusts the clock signal according to the count value.

Abstract: A voltage measurement device includes: a plurality of voltage detection circuits which measure cell voltages of a plurality of cells connected in series. Each of the plurality of voltage detection circuits includes: a device address generating circuit which generates a device address according to a first address assignment command received from a preceding voltage detection circuit located at a preceding stage; and an address assignment command generating circuit which generates a second address assignment command according to the first address assignment command, and sends the second address assignment command to a next voltage detection circuit located at a next stage.

Abstract: A memory device includes a memory array and a memory controller. The memory array includes a first memory bank, a second memory bank, and a third memory bank. The first memory bank includes a first sub memory bank. The second memory bank includes a second sub memory bank. The memory controller, according to a write command from a host, writes first data from the host to the first memory bank and second data to the second memory bank at the same time, and writes a first Hamming weight of the first data to the third memory bank. The second data is the inverse of the first data.

Abstract: A semiconductor device includes: a mounting board; and a semiconductor element disposed on the mounting board via metal bumps, wherein the semiconductor element includes a semiconductor stacked structure and first electrodes, the mounting board includes second electrodes, the metal bumps include a second layer in contact with the second electrodes of the semiconductor element and a first layer located on a side opposite to the second electrodes, an average crystal grain size of crystals included in the second layer is larger than an average crystal grain size of crystals included in the first layer, and the first layer is spaced apart from the second electrodes of the semiconductor element.

Abstract: An image binarization method and an electronic device using the same are provided. The method includes capturing an image by an image capturing device; selecting a target pixel row arranged at the front from one or more unselected first pixel rows among M pixel rows of the image according to a row order by a binarization circuit; performing, by the binarization circuit, a binarization operation on the target pixel row to obtain a binarized pixel row; storing the binarized pixel row to a main memory by the binarization circuit; performing, by the binarization circuit, the binarization operation to the remaining one or more first pixel rows until M binarized pixel rows are obtained, so as to complete the binarization operation.

Abstract: A bus system is provided. The bus system includes a master device, an enhanced serial peripheral interface (eSPI) bus, an SPI bus, a memory device electrically connected to the master device via the SPI bus, and a plurality of slave devices electrically connected to the master device via the eSPI bus. Each of the slave devices has a pin, and the pins of the slave devices are electrically connected together via a control line. After obtaining program code from the memory device via the master device, a first slave device is configured to decrypt the program code according to a first security code, and transmit the program code decrypted by the first security code to the slave devices via the control line, so that the program code decrypted by the first security code is decrypted in the slave devices according to a decryption sequence.

Abstract: An amplifier circuit has an output stage, a first current source, a second current source, a third current source, a fourth current source, and a voltage clamping voltage. The output stage has a first P-type transistor and a first N-type transistor. The voltage clamping circuit receives a first bias voltage and a second bias voltage, and has a first end and a second end. When a second input current is positive current and the input current is a negative current or a zero current, the first end provides a first clamping voltage greater than the first bias voltage to a gate of the first P-type transistor. When the first input current is positive and the second input current is a negative current or zero current, the second end provides a second clamping voltage lower than the second bias voltage to a gate of the first N-type transistor.

Abstract: In a first vertical field-effect transistor in which first source regions and first connectors each of which electrically connects a first body region and a first source electrode are alternately and periodically disposed in a first direction (Y direction) in which a first trench extends, a ratio of LS [?m] to LB [?m] is at least 1/7 and at most 1/3, where LS denotes a length of one of the first source regions in the first direction, and LB denotes a length of one of the first connectors in the first direction, and LB??0.024×(VGS)2+0.633×VGS?0.721 is satisfied for a voltage VGS [V] of a specification value of a semiconductor device, the voltage VGS being applied to a first gate conductor with reference to an electric potential of the first source electrode.

Abstract: A control circuit driving a display panel and including a transmission interface, a charging circuit, an image driving circuit, and a loading management circuit is provided. The transmission interface is configured to be coupled to the display panel. The charging circuit is configured to charge a capacitor. The image driving circuit transforms the voltage of the capacitor into a plurality of driving signals and provides the driving signals to the display panel via the transmission interface. The loading management circuit measures the charge time of the capacitor. In response to the charge time of the capacitor exceeding a threshold value, the loading management circuit asserts a flag to indicate the occurrence of an overload.

Abstract: A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.

Abstract: A detection circuit for detecting a clock signal includes a multiplexer, a digital-to-analog converter, a comparator, and a counter. The multiplexer outputs either a first signal or a second signal as a selection signal. The digital-to-analog converter outputs a reference voltage according to the selection signal. The comparator compares the clock signal to the reference voltage to generate a comparison signal. The counter counts a reference clock signal to generate an overflow signal, and resets the overflow signal according to the comparison signal. The overflow signal indicates the amplitude of the clock signal.

Abstract: A semiconductor device includes: a first latch circuit that includes a first inverting circuit, a second inverting circuit, a third inverting circuit, and a fourth inverting circuit; a first first-type well region; a second first-type well region; and a second-type well region. In a plan view, a distance between a drain of a first-type MOS transistor in the first inverting circuit and a drain of a first-type MOS transistor in the third inverting circuit is longer than a distance between the drain of the first-type MOS transistor in the first inverting circuit and a drain of a first-type MOS transistor in the fourth inverting circuit.

Abstract: A semiconductor laser element includes: an n-type cladding layer disposed above an n-type semiconductor substrate (a chip-like substrate); an active layer disposed above the n-type cladding layer; and a p-type cladding layer disposed above the active layer, in which the active layer includes a well layer and a barrier layer, an energy band gap of the barrier layer is larger than an energy band gap of the n-type cladding layer, and a refractive index of the barrier layer is higher than a refractive index of the n-type cladding layer.

Abstract: A solid-state imaging device includes: a plurality of pixel cells arranged in a matrix. In the solid-state imaging device, each of the plurality of pixel cells includes: a photoelectric converter that generates charge by photoelectric conversion, and holds a potential according to an amount of the charge generated; an initializer that initializes the potential of the photoelectric converter; a comparison section that compares the potential of the photoelectric converter and a predetermined reference signal, and causes the initializer to perform initialization when the potential of the photoelectric converter and the predetermined reference signal match; and a counter that counts a total number of times of initialization performed by the initializer, and outputs a signal corresponding to the total number of times as a first signal indicating an intensity of incident light.

Abstract: A supply voltage detecting circuit has a voltage detection circuit and a current clamping circuit. The voltage detection circuit receives and detects a supply voltage and is used to detect to generate a low-voltage detection signal. When the supply voltage is lower than a set level, the low voltage detection signal output by the voltage detection circuit turns off the current clamping circuit, and a transistor current flowing through the voltage detection circuit is proportional to the supply voltage; and when the supply voltage is higher than or equal to the set level, the low voltage detection signal output by the voltage detection circuit turns on the current clamping circuit, and the current clamping circuit provides a constant current to maintain the operation of the voltage detection circuit, wherein the transistor current flowing through the voltage detection circuit is proportional to the constant current.

Abstract: The present disclosure relates to a low-dropout regulator that limits a quiescent current. It mainly includes an error amplifier, an output switching transistor, a feedback switching transistor, a current duplicating circuit, and a clamping current source. The clamping current source is added between an input voltage and the feedback switching transistor, so that a feedback current outputted by the feedback switching transistor is clamped, and the highest value is only proportional to a current value of the clamping current source. In this way, the quiescent current outputted by the low-dropout regulator is no longer increasing indefinitely in proportional to a load current, which can effectively solve the technical problems of poor stability and decreased efficiency caused by the infinite increase of the quiescent current.

Abstract: An incremental analog-to-digital converter including a first-stage non-delay memorization element and other elements is disclosed. An ending time point of a second reset signal received by the first-stage non-delay memorization element is later than an ending time point of a first reset signal received by the other elements by at least one clock cycle, a reset duration of the first-stage non-delay memorization element is longer than a reset duration of the other element, so that the first-stage non-delay memorization element can be prevented from occurring overshoot or spike on an output thereof, and the incremental analog-to-digital converter can maintain a good signal-to-noise and distortion ratio under the condition that the internal elements has low swing limits.

Abstract: An IC is provided. The IC includes an input pin, a controller, a timer, a first memory, a processor, at least one output pin, an output module coupled to the output pin, and a direct memory access (DMA) device coupled between the output module and the first memory. The controller is configured to provide a first control signal in response to a command from the input pin. The timer is configured to periodically provide a trigger signal according to the first control signal. The processor is configured to store first data in the first memory. The DMA device is configured to obtain the first data from the first memory in response to the trigger signal, and transmit the first data to the output module. The output module is configured to provide the first data to the output pin according to a transmission rate.