Abstract: A coherent optical receiver that receives an optical PSK-modulated signal includes optical elements that combine the optical PSK-modulated signal and an optical local-oscillating (LO) signal and splits the combined optical signals into multiple parts that have a predefined phase offset relative to one another. The receiver further includes at least one thyristor and control circuitry operably coupled to terminals of the at least one thyristor. The control circuitry is configured to receive the multiple parts of the combined optical signals and controls switching operation of the at least one thyristor according to phase offset of optical PSK-modulated signal relative to the optical LO signal.

Abstract: A semiconductor device includes a series of layers formed on a substrate, including a first plurality of n-type layers, a second plurality of layers that form a p-type modulation doped quantum well structure (MDQWS), a third plurality of layers disposed between the p-type MDQWS and a fourth plurality of layers that form an n-type MDQWS, and a fifth plurality of p-type layers. The first plurality of layers includes a first etch stop layer of n-type formed on an n-type contact layer. The third plurality of layers includes a second etch stop layer formed above the p-type MDQWS and a third etch stop layer formed above and offset from the second etch stop layer. The fifth plurality of layers includes a fourth etch stop layer of p-type formed above the n-type MDQWS and a fifth etch stop layer of p-type doping formed above and offset from the fourth etch stop layer.

Abstract: A method of forming an integrated circuit employs a plurality of layers formed on a substrate including i) bottom n-type ohmic contact layer, ii) p-type modulation doped quantum well structure (MDQWS) with a p-type charge sheet formed above the bottom n-type ohmic contact layer, iii) n-type MDQWS offset vertically above the p-type MDQWS, and iv) etch stop layer formed above the p-type MDQWS. P-type ions are implanted to define source/drain ion-implanted contact regions of a p-channel HFET which encompass the p-type MDQWS. An etch operation removes layers above the etch stop layer of iv) for the source/drain ion-implanted contact regions using an etchant that automatically stops at the etch stop layer of iv). Another etch operation removes remaining portions of the etch stop layer of iv) to form mesas that define an interface to the source/drain ion-implanted contact regions of the p-channel HFET. Source/Drain electrodes are on such mesas.

Abstract: A method of forming an integrated circuit employs a plurality of layers formed on a substrate including i) n-type modulation doped quantum well structure (MDQWS) structure with n-type charge sheet, ii) p-type MDQWS, iii) undoped spacer layer formed on the n-type charge sheet, iv) p-type layer(s) formed on the undoped spacer layer, v) p-type etch stop layer formed on the p-type layer(s) of iv), and vi) p-type layers (including p-type ohmic contact layer(s)) formed on the p-type etch stop layer. An etch operation removes the p-type layers of vi) for a gate region of an n-channel HFET with an etchant that automatically stops at the p-type etch stop layer. Another etch operation removes the p-type etch stop layer to form a mesa at the p-type layer(s) of iv) which defines an interface to the gate region of the n-channel HFET, and a gate electrode is formed on such mesa.

Abstract: A semiconductor device includes a substrate supporting a plurality of layers that include at least one modulation doped quantum well (QW) structure offset from a quantum dot in quantum well (QD-in-QW) structure. The modulation doped QW structure includes a charge sheet spaced from at least one QW by a spacer layer. The QD-in-QW structure has QDs embedded in one or more QWs. The QD-in-QW structure can include at least one template/emission substructure pair separated by a barrier layer, the template substructure having smaller size QDs than the emission substructure. A plurality of QD-in-QW structures can be provided to support the processing (emission, absorption, amplification) of electromagnetic radiation of different characteristic wavelengths (such as optical wavelengths in range from 1300 nm to 1550 nm).

Abstract: A method of forming an integrated circuit includes depositing a multilayer metal stack on at least one contact layer of semiconductor material. The multilayer metal stack includes a bottom interface layer formed by a combination of indium and at least one high temperature metal on the at least one contact layer of semiconductor material, at least one barrier layer formed on the bottom interface layer, and a layer formed from at least one high temperature metal on the at least one barrier layer. The metal stack is heated such that indium of the bottom interface layer forms a low resistance interface to contact layer. The at least one barrier layer functions as a barrier to diffusion of indium from the bottom interface layer. Subsequent to the heating, the resultant multilayer metal stack can be patterned to form at least one electrode for a given device of the integrated circuit.

Abstract: A method of forming an integrated circuit employs a plurality of layers supported on a substrate that include i) n-type contact layer, ii) a p-type modulation doped quantum well structure (MDQWS) above the n-type contact layer, iii) n-type MDQWS above the p-type MDQWS, and iv) p-type contact layer(s) above the n-type MDQWS. A feature for a thyristor is defined by a mesa at the p-type contact layer of iv). A first layer of metal is deposited on the feature, which is then etched for at least one other device. Additional layer(s) of metal is deposited on the feature to form cumulative metal layers, which are etched away to form a set of mesas and corresponding electrodes for the thyristor. The cumulative metal layers that cover the feature and contact the mesa at the p-type contact layer of iv) are patterned to form an anode electrode of the thyristor.

Abstract: A transistor device is provided that includes a gate electrode disposed between source and drain electrodes and overlying a quantum dot structure realized by a modulation doped quantum well structure. A potential barrier surrounds the quantum dot structure. The transistor device can be configured for operation as a single electron transistor by means for biasing the gate and source electrodes to allow for tunneling of a single electron from the source electrode through the potential barrier surrounding the quantum dot structure and into the quantum dot structure, and means for biasing the gate and drain electrodes to allow for selective tunneling of a single electron from the quantum dot structure through the potential barrier surrounding the quantum dot structure to the drain electrode, wherein the selective tunneling of the single electron is based upon spin state of the single electron.

Abstract: An assembly includes optical fibers each having a waveguide core, a photonic integrated circuit (IC) that includes in-plane waveguides corresponding to the optical fibers, and a substrate bonded to the photonic IC with grooves that support the optical fibers. The substrate and photonic IC can have metal bumps that cooperate to provide mechanical bonding and electrical connections between the substrate and photonic IC. Portions of the optical fibers supported by the substrate grooves can define flat surfaces spaced from the optical fiber cores. The photonic IC can include passive waveguide structures with a first coupling section that interfaces to the flat surface of a corresponding optical fiber (for evanescent coupling of optical signals) and a second coupling section that interfaces to a corresponding in-plane waveguide (for adiabatic spot-size conversion of optical signals).

Abstract: A coherent optical receiver that receives an optical PSK-modulated signal includes optical elements that combine the optical PSK-modulated signal and an optical local-oscillating (LO) signal and splits the combined optical signals into multiple parts that have a predefined phase offset relative to one another. The receiver further includes at least one thyristor and control circuitry operably coupled to terminals of the at least one thyristor. The control circuitry is configured to receive the multiple parts of the combined optical signals and controls switching operation of the at least one thyristor according to phase offset of optical PSK-modulated signal relative to the optical LO signal.

Abstract: An optical phase detector circuit is provided that is suitable for use in an optical phase lock loop. The optical phase detector includes a first optical flip-flop circuit configured to produce a first digital output based on ON/OFF state of a first digital optical input and a digital electrical control signal. A second optical flip-flop circuit is configured to produce a second digital output based on ON/OFF state of a second digital optical input and the digital electrical control signal. An AND gate is operably coupled to both the first and second optical flip-flops. The AND gate produces the digital electrical control signal for supply to the first and second optical flip-flop circuits according to an AND function of the first and second digital outputs produced by the first and second optical flip-flop circuits.

Abstract: An optoelectronic circuit for producing an optical clock signal that includes an optical thyristor, a waveguide structure and control circuitry. The waveguide structure is configured to split an optical pulse produced by the optical thyristor such that a first portion of such optical pulse is output as part of the optical clock signal and a second portion of such optical pulse is guided back to the optical thyristor to produce another optical pulse that is output as part of the optical clock signal. The control circuitry is operably coupled to terminals of the optical thyristor and receives first and second control signal inputs. The control circuitry is configured to selectively decrease frequency of the optical clock signal based on the first control signal input and to selectively increase frequency of the optical clock signal based on the second control signal input.

Abstract: An optical AND gate is provided that includes an optical thyristor configured to receive first and second digital optical signal inputs. The optical AND gate further includes control circuitry operably coupled to terminals of said optical thyristor. The control circuitry is configured to control switching operation of said optical thyristor in response to the ON/OFF states of the first and second digital optical signal inputs such that the optical thyristor produces a digital output signal that represents the AND function of the first and second digital optical signal inputs. In another aspect, an AND gate is provided that includes a thyristor and control circuitry operably coupled to terminals of the thyristor.

Abstract: An optical XOR circuit that includes a thyristor and control circuitry operably coupled to terminals of the thyristor. The control circuitry is configured to control switching operation of the thyristor in response to the ON/OFF states of two digital optical signal inputs such that the thyristor produces a digital signal output that is the XOR function of the two digital optical signal inputs.

Abstract: An optical flip-flop circuit that includes an optical thyristor configured to receive a digital optical signal input and produce a digital signal output based on the ON/OFF state of the digital optical signal input. The optical flip-flop circuit further includes control circuitry operably coupled to the terminals of the optical thyristor. The control circuitry is configured to control switching operation of the optical thyristor in response to the level of a digital electrical signal input.

Abstract: A semiconductor device that includes an optical resonator spaced from a waveguide structure to provide for evanescent-wave optical coupling therebetween. The optical resonator includes a closed loop waveguide defined by a vertical thyristor structure. In one embodiment, the vertical thyristor structure is formed by an epitaxial layer structure including complementary (both an n-type and a p-type) modulation doped quantum well interfaces formed between an N+ region and a P+ region.

Abstract: A semiconductor device that includes an optical resonator spaced from a waveguide structure to provide for evanescent-wave optical coupling therebetween. The optical resonator includes a closed loop waveguide defined by an epitaxial layer structure that includes at least one quantum well. The semiconductor device also includes circuitry configured to supply an electrical signal that flows within the epitaxial layer structure of the closed loop waveguide. The electrical signal affects charge density in at least quantum well of the closed loop waveguide and controls refractive index of the closed loop waveguide. In one embodiment, the electrical signal is a DC current signal that flows within a vertical thyristor structure of the closed loop waveguide to control refractive index of the closed loop waveguide such that resonance frequency of the closed loop waveguide corresponds to a characteristic wavelength of light.

Abstract: A semiconductor memory device including an array of memory cells (MC) formed on a substrate each realized from a load element and thyristor that define a switchable current path whose state represents a volatile bit value stored by the MC. At least one word line corresponding to a respective row of the array is formed on the substrate and coupled to MC current paths for the corresponding row. Bit lines corresponding to respective columns of the array are formed on the substrate and can be coupled to a modulation doped QW interface of the MC thyristors for the corresponding column. Circuitry is configured to apply an electrical signal to the word line(s) in order to generate current that programs phase change material of the MC load elements into one of a high or low resistive state according to state of the current path of the MCs for non-volatile backup purposes.

Abstract: A semiconductor device suitable for power applications includes a thyristor epitaxial layer structure defining an anode region offset vertically from a cathode region with a plurality of intermediate regions therebetween. An anode electrode is electrically coupled to the anode region. A cathode electrode is electrically coupled to the cathode region. A switchable current path that extends vertically between the anode region and the cathode region has a conducting state and a non-conducting state. An epitaxial resistive region is electrically coupled to and extends laterally from one of the plurality of intermediate regions. An FET is provided having a channel that is electrically coupled to the epitaxial resistive region. The FET can be configured to inject (or remove) electrical carriers into (or from) the one intermediate region via the epitaxial resistive region in order to switch the switchable current path between its non-conducting state and its conducting state.

Abstract: A WDM transmitter and/or receiver optoelectronic integrated circuit includes a plurality of microresonators and corresponding waveguides and couplers that are integrally formed on a substrate. For the WDM transmitter, the microresonators and waveguides are configured to generate a plurality of optical signals at different wavelengths. Each coupler includes a resonant cavity waveguide that is configured to transmit one optical signal from one waveguide to the output waveguide such that the plurality of optical signals are multiplexed on the output waveguide. For the WDM receiver, an input waveguide is configured to provide for propagation of a plurality of optical signals at different wavelengths. Each coupler includes a resonant cavity waveguide that is configured to transmit at least one optical signal from the input waveguide to one waveguide.