Abstract: A charge pump circuit for an optical phase lock loop, which includes first and second optical thyristors configured to receive respective first and second digital optical signal inputs. A first control circuit receives a first digital electrical signal input corresponding to the second digital optical signal input, and a second control circuit receives a second digital electrical signal input corresponding to the first digital optical signal input. The first control circuitry controls switching operation of the first optical thyristor that sources current to a first filter circuit in response to the levels of the first digital optical signal input and the first digital electrical signal input. The second control circuitry control switching operation of the second optical thyristor that sinks current from a second filter circuit in response to the levels of the second digital optical signal input and the second digital electrical signal input.

Abstract: A semiconductor device suitable for power applications includes a thyristor epitaxial layer structure defining an anode region offset vertically from a cathode region with a plurality of intermediate regions therebetween. An anode electrode is electrically coupled to the anode region. A cathode electrode is electrically coupled to the cathode region. A switchable current path that extends vertically between the anode region and the cathode region has a conducting state and a non-conducting state. An epitaxial resistive region is electrically coupled to and extends laterally from one of the plurality of intermediate regions. An FET is provided having a channel that is electrically coupled to the epitaxial resistive region. The FET can be configured to inject (or remove) electrical carriers into (or from) the one intermediate region via the epitaxial resistive region in order to switch the switchable current path between its non-conducting state and its conducting state.

Abstract: A photonic analog-to-digital converter is provided that includes a tunable light source, an optical sampling clock source, an optical splitter and a plurality of optical signal processing channels. The tunable light source produces an optical signal at a variable wavelength corresponding to analog levels of an electrical input signal. The optical sampling clock source produces an optical sampling clock signal that defines a sequence of sampling periods. The optical splitter is operably coupled to the tunable light source. The optical splitter splits the optical signal produced by the tunable light source for supply to the plurality of optical signal processing channels. Each one of the optical signal processing channels includes a photonic filter and corresponding optoelectronic thyristor comparator that is operably coupled to the optical sampling clock source.

Abstract: A monolithic semiconductor device that includes a waveguide structure optically coupled to an optical resonator. The optical resonator is adapted to process light at a predetermined wavelength. The optical resonator includes a closed loop waveguide having a plurality of straight sections that are optically coupled together by bend sections.

Abstract: A semiconductor device employs an epitaxial layer arrangement including a first ohmic contact layer and first modulation doped quantum well structure disposed above the first ohmic contact layer. The first ohmic contact layer has a first doping type, and the first modulation doped quantum well structure has a modulation doped layer of a second doping type. At least one isolation ion implant region is provided that extends through the first ohmic contact layer. The at least one isolation ion implant region can include oxygen ions. The at least one isolation ion implant region can define a region that is substantially free of charge carriers in order to reduce a characteristic capacitance of the device. A variety of high performance transistor devices (e.g., HFET and BICFETs) and optoelectronic devices can employ this device structure. Other aspects of wavelength-tunable microresonantors and related semiconductor fabrication methodologies are also described and claimed.

Abstract: A semiconductor device includes a substrate supporting a plurality of layers that include at least one modulation doped quantum well (QW) structure offset from a quantum dot in quantum well (QD-in-QW) structure. The modulation doped QW structure includes a charge sheet spaced from at least one QW by a spacer layer. The QD-in-QW structure has QDs embedded in one or more QWs. The QD-in-QW structure can include at least one template/emission substructure pair separated by a barrier layer, the template substructure having smaller size QDs than the emission substructure. A plurality of QD-in-QW structures can be provided to support the processing (emission, absorption, amplification) of electromagnetic radiation of different characteristic wavelengths (such as optical wavelengths in range from 1300 nm to 1550 nm).

Abstract: A transistor device is provided that includes a gate electrode disposed between source and drain electrodes and overlying a quantum dot structure realized by a modulation doped quantum well structure. A potential barrier surrounds the quantum dot structure. The transistor device can be configured for operation as a single electron transistor by means for biasing the gate and source electrodes to allow for tunneling of a single electron from the source electrode through the potential barrier surrounding the quantum dot structure and into the quantum dot structure, and means for biasing the gate and drain electrodes to allow for selective tunneling of a single electron from the quantum dot structure through the potential barrier surrounding the quantum dot structure to the drain electrode, wherein the selective tunneling of the single electron is based upon spin state of the single electron.

Abstract: A semiconductor device includes a substrate supporting a plurality of layers that include at least one modulation doped quantum well (QW) structure offset from a quantum dot in quantum well (QD-in-QW) structure. The modulation doped QW structure includes a charge sheet spaced from at least one QW by a spacer layer. The QD-in-QW structure has QDs embedded in one or more QWs. The QD-in-QW structure can include at least one template/emission substructure pair separated by a barrier layer, the template substructure having smaller size QDs than the emission substructure. A plurality of QD-in-QW structures can be provided to support the processing (emission, absorption, amplification) of electromagnetic radiation of different characteristic wavelengths (such as optical wavelengths in range from 1300 nm to 1550 nm).

Abstract: A semiconductor memory device including an array of memory cells (MC) formed on a substrate each realized from a load element and thyristor that define a switchable current path whose state represents a volatile bit value stored by the MC. At least one word line corresponding to a respective row of the array is formed on the substrate and coupled to MC current paths for the corresponding row. Bit lines corresponding to respective columns of the array are formed on the substrate and can be coupled to a modulation doped QW interface of the MC thyristors for the corresponding column. Circuitry is configured to apply an electrical signal to the word line(s) in order to generate current that programs phase change material of the MC load elements into one of a high or low resistive state according to state of the current path of the MCs for non-volatile backup purposes.

Abstract: A semiconductor memory device including an array of memory cells (MC) formed on a substrate each realized from a load element and thyristor that define a switchable current path whose state represents a volatile bit value stored by the MC. At least one word line corresponding to a respective row of the array is formed on the substrate and coupled to MC current paths for the corresponding row. Bit lines corresponding to respective columns of the array are formed on the substrate and can be coupled to a modulation doped QW interface of the MC thyristors for the corresponding column. Circuitry is configured to apply an electrical signal to the word line(s) in order to generate current that programs phase change material of the MC load elements into one of a high or low resistive state according to state of the current path of the MCs for non-volatile backup purposes.