Patents Assigned to Plessey Semiconductors Limited
  • Patent number: 5224055
    Abstract: A machine for circuit design comprising a processor, a configurable logic device and a design tablet device; the processor having a graphics capability and including a display, a design compiler which compiles a graphics representation of the circuit on said display to a set of coded instructions for the setting of the logic device and the design tablet device; wherein the logic device comprises a set of configurable circuit elements in integrated circuit form for providing a hardware representation of some or all of the digital part of the circuit displayed on said display, said coded instructions being operative to control the logic device to appropriately program said circuit elements; and wherein said design tablet device includes a plug board for plugging in discrete electrical components and devices, bus lines coupled to said processor, and wherein said processor is operative to provide appropriate energizing signals to said bus lines to actuate the discrete electrical components and devices.
    Type: Grant
    Filed: October 2, 1990
    Date of Patent: June 29, 1993
    Assignee: Plessey Semiconductors Limited
    Inventors: David L. Grundy, Glenn W. Birchby, Denzil J. Broadhurst
  • Patent number: 5172081
    Abstract: A polarizer arrangement in accordance with the invention includes a circular depolarizer combined in a common component with a linear polarizer. The depolarizer material includes a recess within which a ferrite rod is located, a bias coil being wound around the polarizer and the rod. In another arrangement, a polyrod waveguide feed is also included in the component, being integrated with the circular depolarizer and the linear polarizer.
    Type: Grant
    Filed: April 8, 1991
    Date of Patent: December 15, 1992
    Assignee: Plessey Semiconductors Limited
    Inventors: Timothy A. Gabriel, David G. Spencer
  • Patent number: 5122979
    Abstract: A method and a device (FIG. 2) in which the maximum or the minimum or both of a data set are evaluated by tag propagation through a series of iterations. The number of iterations required is equal to the word size, i.e. the number of bits per word. Iterations may be performed serially using a series of logic stages, as shown, or they may be performed cyclically using a single stage of logic circuitry. For the evaluation of the maximum, a tag is propagated for each word for which a tag has already been propagated from the previous iteration and either the word bit for that iteration is of logic value 1 or if not 1 the word bit for each and every word for that iteration is 0. A tag is propagated throughout all iterations only for the maximum and this tag is then used to select the corresponding data word that is the maximum. The same may be performed for the inverse of each word bit to evaluate the minimum.
    Type: Grant
    Filed: May 29, 1990
    Date of Patent: June 16, 1992
    Assignee: Plessey Semiconductors Limited
    Inventor: Philip F. Culverhouse