Patents Assigned to PLX Technology, Inc.
  • Publication number: 20150281126
    Abstract: A method of transferring data over a switch fabric with at least one switch with an embedded network class endpoint device is provided. At a device transmit driver a transfer command is received to transfer a message. If the message length is less than a threshold the message is pushed. If the message length is greater than the threshold, the message is pulled.
    Type: Application
    Filed: April 3, 2014
    Publication date: October 1, 2015
    Applicant: PLX Technology, Inc.
    Inventors: Jack REGULA, Jeffrey M. DODSON, Nagarajan SUBRAMANIYAN
  • Publication number: 20150254082
    Abstract: A method of remote booting over PCI Express using a synthetic remote boot capability is provided. A management host software system intercepts probe requests from a host and provided information required for a remote boot. The management host software system may include expansion ROM information to support different host architectures. A synthetic device booting capability may be shown to a host, including the expansion ROM information. Additional support for DHCP and TFTP may be provided.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 10, 2015
    Applicant: PLX Technology, Inc.
    Inventors: Rajendran VISHWANATHAN, Nagarajan SUBRAMANIYAN, Jeffrey M. DODSON, Jack REGULA
  • Publication number: 20150127878
    Abstract: Tunneled window connections are utilized in a switch fabric to perform programmed input output transfers. The window connections are based on global IDs. A management entity may enforce the tunneled window connections, improving security.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 7, 2015
    Applicant: PLX Technology, Inc.
    Inventors: Jack REGULA, Nagarajan SUBRAMANIYAN, Jeffrey M. DODSON
  • Patent number: 8880771
    Abstract: A PCIe fabric includes at least one PCIe switch. The fabric may be used to connect multiple hosts. The PCIe switch implements security and segregation measures for host-to-host message communication. A management entity defines a Virtual PCIe Fabric ID (VPFID). The VPFID is used to enforce security and segregation. The fabric ID may be extended to be used in switch fabrics with other point-to-point protocols.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: November 4, 2014
    Assignee: PLX Technology, Inc.
    Inventors: Nagarajan Subramaniyan, Jack Regula, Jeffrey Michael Dodson
  • Publication number: 20140237156
    Abstract: PCIe is a point-to-point protocol. A PCIe switch fabric has multi-path routing supported by adding an ID routing prefix to a packet entering the switch fabric. The routing is converted within the switch fabric from address routing to ID routing, where the ID is within a Global Space of the switch fabric. Rules are provided to select optimum routes for packets within the switch fabric, including rules for ordered traffic, unordered traffic, and for utilizing congestion feedback. In one implementation a destination lookup table is used to define the ID routing prefix for an incoming packet. The ID routing prefix may be removed at a destination host port of the switch fabric.
    Type: Application
    Filed: March 31, 2014
    Publication date: August 21, 2014
    Applicant: PLX Technology, Inc.
    Inventors: Jack REGULA, Jeffrey M. DODSON, Nagarajan SUBRAMANIYAN
  • Patent number: 8797857
    Abstract: In a first embodiment of the present invention, a method for handling a Transaction Layer Packets (TLPs) from devices in a switch is provided, the method comprising: subtracting a first number of credits from a credit pool associated with a first port on which a first device is connected; determining if the amount of credits in the credit pool associated with the first port is less than a first predetermined threshold; and if the amount of credits in the credit pool associated with the first port is less than the first predetermined threshold, assigning a second number of credits from a shared credit pool to the credit pool associated with the first port.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: August 5, 2014
    Assignee: PLX Technology, Inc.
    Inventors: Jeffrey Michael Dodson, Joe Keirouz
  • Patent number: 8785246
    Abstract: A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: July 22, 2014
    Assignee: PLX Technology, Inc.
    Inventors: Duc Anh Vu, Jayalakshmana Kumar Pragasam, Vijay Meduri, Seyed Attaran, Michael J. Grubisich, Syed Ahmed, Aniket Singh
  • Patent number: 8738812
    Abstract: A controller controls transfer of commands and storage data over a databus to a data storage device. The controller comprises a memory arranged to store a queue of commands prior to the commands being transferred over the databus. The controller identifies data access commands in the queue that specify the same type of data access and contiguous ranges of addresses. A concatenated data access command is transferred in place of so identified data access commands, the concatenated data access command specifying the same type of data access and the overall range of addresses. This improves the rate of data transfers.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: May 27, 2014
    Assignee: PLX Technology, Inc.
    Inventors: Matthew Stephens, Shigekatsu Tateno
  • Publication number: 20140122765
    Abstract: A PCIe fabric includes at least one PCIe switch. The fabric may be used to connect multiple hosts. The PCIe switch implements security and segregation measures for host-to-host message communication. A management entity defines a Virtual PCIe Fabric ID (VPFID). The VPFID is used to enforce security and segregation. The fabric ID may be extended to be used in switch fabrics with other point-to-point protocols.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: PLX TECHNOLOGY, INC.
    Inventors: Nagarajan SUBRAMANIYAN, Jack REGULA, Jeffrey Michael DODSON
  • Patent number: 8683285
    Abstract: In a first embodiment of the present invention, a method for error-correcting in a parallel interconnect transmitting device is provided, the method comprising: detecting a frame transition in a transmission from the transmitting device to a parallel interconnect receiving device; tracking time between the frame transition and a transition of a response signal corresponding to the frame transition received from the receiving device; detecting an error in the transmission; and restarting a portion of the transmission in response to the error, wherein the size of the portion of the transmission to restart is based upon the tracked time between the frame transition and the transition of a response signal corresponding to the frame transition.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: March 25, 2014
    Assignee: PLX Technology, Inc.
    Inventor: Jack Regula
  • Publication number: 20140035106
    Abstract: A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit.
    Type: Application
    Filed: August 3, 2012
    Publication date: February 6, 2014
    Applicant: PLX TECHNOLOGY, INC.
    Inventors: Duc Anh VU, Jayalakshmana Kumar PRAGASAM, Vijay MEDURI, Seyed ATTARAN, Michael J. GRUBISICH, Syed AHMED, Aniket SINGH
  • Patent number: 8645605
    Abstract: A method is provided comprising: enumerating a group of available virtual functions corresponding to the physical function; mapping the group of available virtual functions to a non-transparent port of the switch by creating a copy of a configuration space for the physical function while assigning unique vendor and device identifications for different classes of devices, wherein the mapping creates a pseudo physical function exposing a subset of the SR-IOV capability from the configuration space for the physical function; receiving a request to access the physical function from the single host; and providing the pseudo physical function to the single host for loading on the single host, in response to the receiving of the request, wherein the pseudo physical function is designed to call management functions of the single host to enable the group of available virtual functions in a local hierarchy of the single host.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: February 4, 2014
    Assignee: PLX Technology, Inc.
    Inventors: Nagarajan Subramaniyan, Jack Regula, Jeffrey Michael Dodson
  • Publication number: 20130308656
    Abstract: Embodiments of methods, apparatuses, and systems for signal processing of multiple input signals to control peak amplitudes of a combined signal are disclosed. One method includes receiving a plurality of input signals, generating a combined signal, the combined signal comprising a plurality of sub-channels, wherein each sub-channel includes a representation of at least a portion of at least one of the plurality of input signals, and processing the representation of the least a portion of the at least one of the plurality of input signals of at least one of the sub-channels, to reduce a peak-to-average-power ratio (PAR) of the combined signal.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 21, 2013
    Applicant: PLX TECHNOLOGY, INC.
    Inventors: Moshe Malkin, Dimitry Taich, Jose Tellado
  • Patent number: 8554976
    Abstract: A method for processing an incoming command destined for a target is provided, comprising: determining if the incoming command is a data command or a management command; forwarding the incoming command to a storage management component of the target when the incoming command is a management command; when the incoming command is a data command: determining if a disk command queue on the target is full; sending the incoming command to the disk command queue when the disk command queue is not full; when the disk command queue is full: starting a timer, the timer having a predetermined length; sending the incoming command to the disk command queue when the disk command queue becomes not full prior to the expiration of the timer; and sending a rejection of the incoming command to the host only if, upon expiration of the timer, if the disk command queue is still full.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: October 8, 2013
    Assignee: PLX Technology, Inc.
    Inventors: Neil Buxton, Philip David Rose
  • Patent number: 8553683
    Abstract: In a first embodiment of the present invention, a non-blocking switch fabric is provided comprising: a first set of intra-domain switches; a second set of intra-domain switches; a set of inter-domain switches located centrally between the first set of intra-domain switches and the second set of intra-domain switches, wherein each of the ports of each of the inter-domain switches is connected to an intra-domain switch from the first or second set of intra-domain switches.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: October 8, 2013
    Assignee: PLX Technology, Inc.
    Inventor: Jack Regula
  • Patent number: 8548011
    Abstract: In accordance with a first embodiment of the present invention, a method for improving synchronization of communications between a first port and a second port is provided, the method performed at the first port and comprising: inserting skip symbols into a transmission stream for transmissions from the first port to the second port, wherein the skip symbols are inserted at a first average frequency level; detecting a lack of synchronization between the first port and the second port; and inserting skip symbols into the transmission stream at a second average frequency level greater than the first average frequency level in response to the detecting.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: October 1, 2013
    Assignee: PLX Technology, Inc.
    Inventor: Andrew Gordon Green
  • Patent number: 8543890
    Abstract: In a first embodiment of the present invention, a method for operating a midpoint device utilizing an Input/Output (I/O) interconnect is provided, wherein the midpoint device contains a plurality of ports, the method comprising: receiving a request to initiate a session between a device on a first port of the midpoint device and a device on a second port of the midpoint device; retrieving information regarding whether the first port supports a feature, and information regarding whether the second port supports the feature; and when the first port supports the feature and the second port does not support the feature, permitting the session to be initiated, such that communications between the first device and the second device are performed partially using the feature, independently of support of the feature on other ports.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: September 24, 2013
    Assignee: PLX Technology, Inc.
    Inventor: Jeffrey Michael Dodson
  • Patent number: 8521941
    Abstract: In a first embodiment of the present invention, a method for multi-root sharing of a plurality of single root input/output virtualization (SR-IOV) endpoints is provided, the method comprising: CSR redirection to a management processor which either acts as a proxy to execute the CSR request on behalf of the host or filters it and performs an alternate action, downstream routing of memory mapped I/O request packets through the switch in the host's address space and address translation with VF BAR granularity, upstream routing of requests originated by I/O devices by table lookup indexed by Requester ID, and requester ID translation using a fixed local-global RID offset.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: August 27, 2013
    Assignee: PLX Technology, Inc.
    Inventor: Jack Regula
  • Publication number: 20130214829
    Abstract: In a first embodiment of the present invention, a clock recovery system is provided comprising: a phase comparator; an integrator coupled to the phase comparator; a numerically controlled oscillator coupled to the integrator; and a mixer coupled to the numerically controlled oscillator and to the phase comparator.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 22, 2013
    Applicant: PLX Technology, Inc.
    Inventors: Niranjan TALWALKAR, Moshe MALKIN
  • Patent number: 8504755
    Abstract: A bridge device for connecting a USB 3 host device with a plurality of downstream, non-USB 3 mass storage devices, such as SATA or PATA devices. The bridge device comprises an embedded hub having a plurality of internal USB 3 devices. The internal USB 3 devices do not have a physical USB 3 interface. The bridge device also has at least one downstream physical non-USB 3 device, to which a mass storage device may be attached. The internal USB 3 devices enable the host device to be presented with a plurality of USB 3 devices. This, in turn, allows transfer to the plurality of downstream physical non-USB 3 devices, via the internal USB 3 devices at an increased rate. The bridge may also include a downstream physical USB 3 interface. This can allow multiple bridge devices to be connected together in a cascade.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: August 6, 2013
    Assignee: PLX Technology, Inc.
    Inventors: Duncan Beadnell, Neil Buxton, Gary Calder