Abstract: An apparatuses and methods of setting power back-off of a master transceiver and a slave transceiver is disclosed. One example of a method includes the master transceiver determining a master power back-off, and the slave transceiver determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off. One example of an apparatus includes a master transceiver and slave transceiver system. The slave transceiver is connected to the master transceiver through a cable. The master transceiver includes means for determining a master power back-off. The slave transceiver includes means for determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off.

Abstract: An apparatus and method of controlling activation of electronic circuitry of data ports of a communication system is disclosed. One method includes a first data port detecting a lack of data for transmission to a second data port. At least one of the first data port and a second data port deactivate electronic circuitry of at least one of the first and second data ports upon detection of the lack of data. The first and second data ports maintain synchronization with each other while the electronic circuitry is deactivated by periodically exchanging synchronization test patterns. At least one of the first data port and the second data port transmit an alert to the other of the first and second data port when data for communication is detected. The other of the first data port and the second data port activate electronic circuitry upon receiving the alert. At least one of the first data port and the second data port transmit data.

Abstract: In a first embodiment of the present invention, a method for handling a Transaction Layer Packets (TLPs) from devices in a switch is provided, the method comprising: subtracting a first number of credits from a credit pool associated with a first port on which a first device is connected; determining if the amount of credits in the credit pool associated with the first port is less than a first predetermined threshold; and if the amount of credits in the credit pool associated with the first port is less than the first predetermined threshold, assigning a second number of credits from a shared credit pool to the credit pool associated with the first port.

Abstract: An apparatus and method of setting power back-off of a master transceiver and a slave transceiver is disclosed. The method includes the master transceiver determining a master power back-off, and the slave transceiver determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off.

Abstract: A voltage controlled oscillator and a load cell circuit usable in VCO are provided. The VCO features an internal compensation for process, voltage and temperature using a replica of half of the oscillating stage. The load cell circuit comprises a bias transistor to drain a predetermined current from the oscillating stage, a control transistor to vary resistance offered by it responsive to a control voltage applied and a resistor adapted to provide a clamp resistance.

Abstract: A controller for controlling the operation of a hard disk drive is capable of generating a random number using the hard disk drive. Initially the hard disk drive is disabled from performing a read-ahead operation. Random addresses on the hard disk drive are generated from the output of the pseudo-random number generator. Read-verify commands is sent to the hard disk drive to perform a read-verify operation of reading and verifying the data stored in the sectors of the hard disk drive at the random addresses without returning the data. The disk access times taken by the hard disk drive to access the sectors are measured. A deskewing process is performed on a plural number of disk access time measurements to generate a random number.

Abstract: In a first embodiment of the present invention, a method for handling a Transaction Layer Packets (TLPs) from devices in a switch is provided, the method comprising: subtracting a first number of credits from a credit pool associated with a first port on which a first device is connected; determining if the amount of credits in the credit pool associated with the first port is less than a first predetermined threshold; and if the amount of credits in the credit pool associated with the first port is less than the first predetermined threshold, assigning a second number of credits from a shared credit pool to the credit pool associated with the first port.

Abstract: In one embodiment, a method for controlling reads in a computer input/output (I/O) interconnect is provided. A read request is received over the computer I/O interconnect from a first device, the request requesting data of a first size. Then it is determined whether fulfilling the read request would cause the total size of a completion queue to exceed a first predefined threshold.

Abstract: In a USB device, virtual endpoint capability allows a number of physical endpoints in the device to support a larger number of data pipes at logical endpoints requested by the host. This is done by re-assigning physical endpoints to support the logical endpoint requested by the host. The logical endpoints and their corresponding data pipes may be served in a round robin scheme.

Abstract: A system for communication on a chip. The system includes an on-chip communication bus including plural tracks, and a plurality of stations that couple a plurality of on-chip components to the on-chip communication bus, whereby the plurality of on-chip components use the tracks to communicate. Each station preferably includes an initiator that requests permission to transmit outgoing data over a track to another station and that transmits the outgoing data, an arbiter that evaluates requests from other stations and selects a track on which to receive incoming data, and a target that receives the incoming data. The initiator can be connected to a grant multiplexor for selecting a grant line, with the grant multiplexor further including plural smaller multiplexors distributed across the chip. Likewise, the arbiter can be connected to a track multiplexor for selecting a track, with the track multiplexor further including plural smaller multiplexors distributed across the chip.

Abstract: The disclosure relates to apparatus and methods that provide a system interconnect for transporting cells between nodes on a dual counter-rotating ring network, including a link selection register for selecting the shortest path to a destination node, use of a fault tolerant frequency reference to synchronize node clocks, interconnect initialization, multi-ring topologies along with an addressing schema and ring-to-ring couplers. The disclosure also discusses flow control of cells leaving nodes, coupling cells from one ring to another, and use of such an interconnect as a bus replacement.

Abstract: The invention discloses methods and apparatus for broadcasting information across an interconnect that includes a plurality of nodes each connected to its adjacent node(s) using one or more links. The nodes can emit cells containing transaction sub-actions onto the links. As a node receives a cell the node retransmits the cell onto other links as the cell is being received. Thus, reducing the latency imposed by the node. The node also captures the transaction sub-action while it the cell is retransmitted. The node responds to the transaction sub-action by manipulating shared handshake lines that are bussed with the other nodes. The invention enables snooping cache protocols to be successfully used in a larger multi-processor computer system than the prior art.

Abstract: The invention discloses methods and apparatus for broadcasting information across an interconnect that includes a plurality of nodes each connected to its adjacent node(s) using one or more links. The nodes can emit cells containing transaction sub-actions onto the links. As a node receives a cell the node retransmits the cell onto other links as the cell is being received. Thus, reducing the latency imposed by the node. The node also captures the transaction sub-action while it the cell is retransmitted. The node responds to the transaction sub-action by manipulating shared handshake lines that are bussed with the other nodes. The invention enables snooping cache protocols to be successfully used in a larger multi-processor computer system than the prior art.

Abstract: The disclosure relates to apparatus and methods that provide a system interconnect for transporting cells between nodes on a dual counter-rotating ring network, including a link selection register for selecting the shortest path to a destination node, use of a fault tolerant frequency reference to synchronize node clocks, interconnect initialization, multi-ring topologies along with an addressing schema and ring-to-ring couplers. The disclosure also discusses flow control of cells leaving nodes, coupling cells from one ring to another, and use of such an interconnect as a bus replacement.

Abstract: The disclosure relates to apparatus and methods that provide a system interconnect for transporting cells between nodes on a dual counter-rotating ring network, including a link selection register for selecting the shortest path to a destination node, use of a fault tolerant frequency reference to synchronize node clocks, interconnect initialization, multi-ring topologies along with an addressing schema and ring-to-ring couplers. The disclosure also discusses flow control of cells leaving nodes, coupling cells from one ring to another, and use of such an interconnect as a bus replacement.

Abstract: A binary relative delay line device having two delay lines, each of which delays, during a time interval, an input signal by a substantially equal amount of time. Each delay line requires a settling time before it is selected during a next time interval. A selection and delay determining circuit is coupled to the two delay lines to select one of them to provide an output signal. A clock is coupled to the selection and delay determining circuit to operate the selection and delay determining circuit at a lower frequency than the frequency of the input signal, the lower frequency being chosen so that any selected delay line has settled before it is selected.