Patents Assigned to Qlogic Corporation
  • Patent number: 9281953
    Abstract: Method and system for a network device are provided. The device includes a port for receiving a multicast packet and a multicast data structure for maintaining information regarding a multicast group to which the multicast packet is to be sent. When the port is a part of a link aggregation group (LAG), then any port that is a member of the LAG is removed from the multicast group such that the multicast packet is not sent to any member of the LAG.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: March 8, 2016
    Assignee: QLOGIC, Corporation
    Inventor: Frank R. Dropps
  • Patent number: 9282000
    Abstract: Method and system for configuring a port of a network device are provided. One method for a port of a network device communicating with another network device port includes reading manufacturing, license and user provided port configuration data by a processor of the network device; obtaining capabilities information for the port by the processor of the network device from an external pluggable media device; setting port configuration data based on the capabilities information obtained from the external pluggable media; executing auto-negotiation on the port, when enabled and obtaining configuration data from the other port; determining that enough data is available to set port configuration; attempting to configure the port by using a highest permissible bandwidth configuration when enough data is available to set the port configuration; and setting port configuration based on the attempt to configure the port to operate when a link connected to the port is operational.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: March 8, 2016
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Craig M. Verba, Leo J. Slechta, Jr.
  • Patent number: 9282046
    Abstract: Network device and associated methods are provided. The network device includes a plurality of base-ports, each base-port coupled to a plurality of network links and each base-port includes a plurality of sub-ports configured to operate as independent ports for sending and receiving information. Each network link is coupled to a smoothing first in-first out (FIFO) memory module that is used to temporarily store information at a first clock rate and information is read from the smoothing FIFO at a second clock. A sub-port can include one network link or more than one network link for receiving information from another device. A controller module monitors the smoothing FIFO for each network link to insert or delete characters from each of the smoothing FIFO based on a sub-port configuration for maintaining an order in which information is received for the sub-port.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 8, 2016
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Ernest G. Kohlwey
  • Patent number: 9264383
    Abstract: Method and system for a network device having a plurality of ports for sending and receiving information is provided. The device includes a global quality of service (QOS) module for receiving QOS information from a plurality of QOS modules regarding bandwidth used by the plurality of ports for sending information. For selecting a request from among a plurality of pending requests from the plurality of ports to transmit information, the global QOS module adds bandwidth consumed by the plurality of ports when the ports belong to a non-local link aggregation group (LAG). The global QOS module uses local QOS information from a same QOS bin assigned to the plurality of ports, when the plurality of ports belong to a local LAG.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: February 16, 2016
    Assignee: QLOGIC, Corporation
    Inventor: Frank R. Dropps
  • Patent number: 9256562
    Abstract: Machine implemented method and system are provided. A processor for a computing device allocates an address range with an address to write to an intermediate storage location. The processor configures a device communicating with the computing device for writing information at the intermediate storage location and at a plurality of storage locations. The computing device sends the address for the intermediate storage location with data that needs to be written at one of the plurality of storage locations with an identifier identifying the one of the plurality of storage locations; and the device first writes the data at the intermediate storage location and then updates the one of the plurality of storage locations identified by the identifier.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: February 9, 2016
    Assignee: QLOGIC, Corporation
    Inventors: Kanoj Sarcar, Madhusudhan Harigovindan Thekkeettil
  • Patent number: 9256491
    Abstract: A device having a storage location for receiving an original data and a corresponding original error correction code (ECC) is provided. The device includes ECC modification pattern generator logic for comparing modified data and the original data for generating a pattern for modifying the original ECC and ECC modification logic for modifying the original ECC based on the pattern.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: February 9, 2016
    Assignee: QLOGIC, Corporation
    Inventor: Frank R. Dropps
  • Patent number: 9253120
    Abstract: Network device for sending and receiving information is provided. The network device includes a port having a receive segment for receiving information and a transmit segment for transmitting information. The port can be configured to operate as an independent port using a single link operating at 25 gigabits per second.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: February 2, 2016
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Bruce A. Klemin, Edward C. McGlaughlin
  • Patent number: 9229893
    Abstract: Methods and systems for DMA operations are provided. A plurality of control blocks are stored at a memory of a receive module of a device coupled to a computing device, where the control blocks store information regarding data packets stored at a receive buffer accessible to the receive module. At least a first control block and a second control block are retrieved from the memory; and a first DMA register set is assigned to the first control block and a second DMA register set is assigned to the second control block. The first control block and the second control block are simultaneously pre-processed to configure the first DMA register set and the second DMA register set.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: January 5, 2016
    Assignee: QLOGIC, Corporation
    Inventors: Chuong HoangMinh Pham, Dharma R. Konda
  • Patent number: 9229791
    Abstract: An adapter for high speed multiple buffer allocation is provided. The adapter is configured with logic to search a data buffer availability vector corresponding to data buffer storage elements from low priority to high priority and from high priority to low priority in parallel thereby enabling multiple data buffers to be located in a single path and reducing the impact of pipelining.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: January 5, 2016
    Assignee: QLOGIC, Corporation
    Inventor: Madhusudhan Harigovindan Thekkeettil
  • Patent number: 9232005
    Abstract: An adapter for processing requests from a computing device is provided. The adapter includes a processor executing: a storage protocol driver for interfacing with a storage protocol controller that communicates with a storage device of a storage area network (SAN) via a port for providing SAN connectivity to the adapter; and a storage driver for interfacing with a solid state storage device managed by the adapter and available to the computing device as a local caching device.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: January 5, 2016
    Assignee: QLOGIC, Corporation
    Inventors: Shishir Shah, Ajmer Singh, Charles Micalizzi, Jr., Sudhir T. Ponnachana
  • Patent number: 9223518
    Abstract: Method and system for processing a read request are provided. The first adapter receives the read request from a client to read data using a logical object managed by a second adapter. The first adapter is configured to generate a vendor unique command descriptor block for the second adapter to obtain the data and write the data at a location specified by the read request. The second adapter is configured to retrieve the data from a storage location specified by the logical object and writing the data at the location specified by the read request; and notifies the first adapter after writing the data.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: December 29, 2015
    Assignee: QLOGIC, Corporation
    Inventor: Normin A. Emralino
  • Patent number: 9225808
    Abstract: Systems and methods for a network device are provided. The network device includes a receive segment for receiving frames for a plurality of sub-ports complying with the plurality of protocols. A frame complying with a first protocol is received at a first clock rate for a first sub-port and a frame complying with a second protocol is received at a second clock rate for a second sub-port. To process frames regardless of protocol type, the receive segment adds an internal header for the frame complying with the first protocol and for the frame complying with the second protocol. The internal header indicates a frame protocol type and identifies the first sub-port and the second sub-port such that the same logic can be used to process the frame complying with the first protocol and the frame complying with the second protocol.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: December 29, 2015
    Assignee: QLOGIC, Corporation
    Inventor: Frank R. Dropps
  • Patent number: 9225672
    Abstract: Methods and systems for packet grouping in a network are provided. A packet is received at a receive segment of a port of a first network device for transmission to a destination port of a second network device. The port determines if the packet is a start packet of a packet sequence. When the packet is not the start packet of the packet sequence, the port determines whether the packet has a destination that is the same as a destination of a last prior packet. When the packet is for the same destination, a grouping count is increased and the packet priority is elevated.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: December 29, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Craig M. Verba
  • Patent number: 9172586
    Abstract: A computing device having a processor for executing an application for generating an input/output (I/O) request for writing data to a logical object presented to the application; and a device interfacing with the computing device having a processor for generating a single I/O command for writing data in response to the I/O request and writing a tag that is associated with the data are provided. The tag includes an identifier for the logical object used for writing the data at a storage device and a logical address for a location at the storage device where the data is written. Furthermore, the tag is stored at a memory device of the device, while the data is stored at a local caching device, at a storage area network (SAN) storage device or both.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: October 27, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Shishir Shah, Ajmer Singh
  • Patent number: 9172661
    Abstract: Method, system and network device for programming lane alignment markers are provided. The method includes configuring the first port having a plurality of sub-ports, as at least a dual lane port where each lane of the dual lane port is configured to receive and transmit frames; negotiating with the first network device to determine a lane alignment marker that is acceptable by the first network device; and programming the first port to identify the lane alignment marker associated with the vendor of the first network device for processing frames received from the first network device and transmitted to the first network device.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: October 27, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Ernest G. Kohlwey, Leo J. Slechta, Jr.
  • Patent number: 9172655
    Abstract: System and methods for providing quality of service (QOS) in networks. The method includes determining whether a transmit segment of a port of a network device has received a grant from a scheduler to transmit a packet. The port includes a plurality of sub-ports that share the transmit segment to transmit packets and a receive segment to receive packets. When the transmit buffer has received the grant, a virtual queue associated with the grant is mapped to a QOS bin that includes a minimum bandwidth limit threshold value, a maximum bandwidth threshold value, and a counter for counting actual bandwidth consumed. The QOS bin monitors bandwidth consumed by a source traffic group for adjusting QOS priority and the source traffic group includes the virtual queue.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: October 27, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Gary M. Papenfuss
  • Patent number: 9172602
    Abstract: Methods and systems for negotiating between a first network device and a second network device connected to a network, is provided. The method determining if a first port of the first network device having a plurality of Sub-Ports, is auto-negotiation enabled; wherein the plurality of Sub-Ports can be configured to operate independently as a port for sending and receiving information using one of a plurality of network links at a plurality of rates complying with a plurality of protocols; configuring any one or more of the Sub-Ports as one quad lane, two dual lane, one dual lane and two single lane, or four single lane ports; determining if lanes of the first port are physically swapped by identifying which one or more of the Sub-Ports will operate as a lane 0 for communicating with a particular lane 0 of the second network device; and processing auto-negotiation on all lanes.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: October 27, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Ernest G. Kohlwey
  • Patent number: 9170880
    Abstract: Method and system for a network device are provided. The method includes generating error correction code (ECC) for writing data to a ternary content addressable memory used by the network device; storing the ECC code and the data at the TCAM; generating an ECC for a search key, used for searching the TCAM; and detecting any error in the stored data by using the search key with appended ECC.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: October 27, 2015
    Assignee: QLOGIC, Corporation
    Inventor: Frank R. Dropps
  • Patent number: 9164947
    Abstract: A system having an initiator adapter coupled to a computing system and communicating with a target adapter coupled to a target controller managing a plurality of storage devices is provided. The initiator adapter initiates an input/output (I/O) request for the target adapter; assigns an exchange identifier for processing the I/O request and embeds a cookie in the exchange identifier for performing a function. The target adapter then sends a response to the I/O request to the initiator adapter with the exchange identifier and the cookie; and the initiator adapter extracts the cookie from the exchange identifier received from the target adapter.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: October 20, 2015
    Assignee: QLOGIC, Corporation
    Inventor: Gaurav Borker
  • Patent number: 9164913
    Abstract: Machine implemented method and system for processing a write request for a copy on write (COW) enabled write operation to write to a logical unit number (LUN) for which a replicated LUN exists is provided. An adapter coupled to a computing system and interfacing with the LUN and the replicated LUN receives the write request having an indicator indicating that the write request is for the COW enabled write operation. The adapter issues a read request to the LUN to read previous information from the LUN; temporarily stores the previous information at a memory storage location of the adapter; writes the previous information to the replicated LUN; writes the information based on the write request to the LUN; and notifies the computing system indicating that the write request for the COW enabled write operation has been completed.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: October 20, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Deepak Tawri, Sanjeev Jorapur