Patents Assigned to Qlogic Corporation
  • Patent number: 9154569
    Abstract: Method and system for a first network device communicating with a second network device are provided. A first duration is compared with a stored maximum pause delay value and the first duration is set as a new maximum pause delay value when the first duration is greater than the maximum pause delay value. The new maximum pause delay value is compared with a programmed pause delay threshold value that indicates a duration after which the first network device will stop sending frames, after the pause frame is received by the first network device. A pause threshold value and the programmed pause delay threshold value are adjusted based on the comparison between the new maximum pause delay value and the programmed pause delay threshold value.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: October 6, 2015
    Assignee: QLOGIC, Corporation
    Inventor: Frank R. Dropps
  • Patent number: 9154455
    Abstract: Method and system for a network device having a plurality of queues for receiving information from another device is provided. A frame is received at a receive queue of the network device. The process determines that the receive queue of the network device has reached a programmable threshold value and determines if a frame waiting at the receive queue is eligible for being dropped. The frame is eligible for being dropped when a drop eligibility bit is set in a frame header by a sender of the frame, when a priority established for the frame indicates that the frame is drop eligible and when a destination for the frame is congested.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 6, 2015
    Assignee: QLOGIC, Corporation
    Inventor: Frank R. Dropps
  • Patent number: 9143415
    Abstract: Machine implemented method and system of detecting a loss of sync at a port of a network device coupled to a port of another device is provided. The port includes logic configured to detect that a special character has not been received by the port for a programmable duration; and generates a signal for a processor of the network device indicating a loss of sync between the port of the network device and the port of the other device.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: September 22, 2015
    Assignee: QLOGIC, Corporation
    Inventors: David T. Kwak, Oscar L. Grijalva
  • Patent number: 9118610
    Abstract: Method and system for a network device having a plurality of queues for receiving information from another device is provided. The device determines if all requests for transferring frames from the plurality of queues have been sent to an arbitration module that arbitrates and selects requests for transmitting frames associated with the selected requests. When all requests have not been selected, then selecting a tag having information regarding a next frame, when a destination of the next frame or a transmit queue of the next frame does not match a destination or a transmit queue of any other frame for which a request has been sent to the arbitration module.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: August 25, 2015
    Assignee: QLOGIC, Corporation
    Inventor: Frank R. Dropps
  • Patent number: 9118586
    Abstract: A method and system for routing frames based on a port's speed using a switch element. The method includes receiving a portion of a frame in a receive buffer of a port; determining a frame length threshold value; and setting up a status bit based on the port's speed, the frame length threshold value and an amount of the frame received. The status bit is sent to a transmit segment of the switch element and the frame length threshold value is proportional to the port's speed. Also, if the receive buffer is almost full when the frame arrives at the receive port, then a cut status is based on the frame's end of frame (“EOF”) value.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: August 25, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Craig M. Verba, Gary M. Papenfuss
  • Patent number: 9100334
    Abstract: Machine implemented method and system for processing frames received by a network device from another network device via a network link are provided. The network device is configured to maintain a data structure to determine a tag size of a tag received in a frame header of a frame received by the network device; determine if the tag size is less than a fixed programmable size; insert a blank character to increase the tag size to the programmable size; and process the frame with the tag having the programmable size.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: August 4, 2015
    Assignee: QLOGIC, Corporation
    Inventors: David T. Kwak, Ali A. Khwaja, Frank Palumbo
  • Patent number: 9094343
    Abstract: Method and system for network communication including identifying a first network port to be taken offline. Before taking the first network port offline, processing any pending packet tag for the first network port. The method further includes taking the first network port offline; storing a packet tag destined for the first network port at the second network port, while the first network port is offline; bringing the first network port online; and routing the packet tag stored at the second network port, while the first network port was offline; wherein the packet tag is routed from the second network port to the first network port.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: July 28, 2015
    Assignee: QLOGIC, Corporation
    Inventors: James A. Kunz, Craig M. Verba, Thomas R. Prohofsky
  • Patent number: 9094333
    Abstract: A network device is provided. The network device includes a port complex having a plurality of ports configured to operate at different operating speeds for sending and receiving information complying with different protocols. The network device further includes a processor complex having a plurality of processors for processing information complying with different protocols and received by the plurality of ports; and a message queuing system (MQS) for managing messages for the plurality of processors regarding the received information complying with different protocols. Each processor can process information complying with any of the different protocols.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: July 28, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Bruce A. Klemin, Jerald K. Alston, Derek J. Rohde
  • Patent number: 9094294
    Abstract: Method and system for reporting out-of-credit condition for a network device connected to a network. An indication to an out-of credit logic is provided that a first sub-port operating using a first protocol is out of credit to transmit information from a transmit segment. The first sub-port is a part of a base-port that includes a plurality of sub-ports that can be configured to operate at more than one operating speed to process packets complying with different protocols. The out-of-credit logic determines when the first sub-port is out-of-credit for a threshold period of time, and reports that the sub-port is out-of-credit to a processor of the network device.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: July 28, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Bret E. Indrelee, Leo J. Slechta, Jr., Gary M. Papenfuss, Edward C. Ross
  • Patent number: 9071558
    Abstract: Methods and systems for routing frames are provided. A system includes an initiator operationally coupled to a first switch that is coupled to a second switch. The first switch includes a plurality of ports for sending and receiving frames and includes a routing table that identifies a port identifier steering table based on an area field of a frame header of a frame received by the first switch. The first switch also includes a plurality of port identifier tables, where each port identifier table is associated with a unique area field and identifies a same port of the first switch for a plurality of area fields. The second switch stores an area steering table with port identification information associated with an area field of a frame header of a frame received by the second switch and a same port of the second switch is assigned to multiple area fields.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: June 30, 2015
    Assignee: QLOGIC Corporation
    Inventor: Edward C. McGlaughlin
  • Patent number: 9071544
    Abstract: A management request complying with a first protocol is generated by a management application executed by a computing system coupled to a network element. A processor executable agent encapsulates a management request using a second protocol. The encapsulated management request is transmitted using a third protocol via a link used by the computing system to send input/output requests for reading and writing data to a storage device. The management request is de-encapsulated to provide the management request complying with the first protocol to a management module of the network element. The management module of the network element prepares a response to the management request complying with the first protocol. A processor executable service at the network element encapsulates the response using the second protocol. The encapsulated response is transmitted to the computing system using the third protocol. The response complying with the first protocol is extracted from the encapsulated response.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: June 30, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Stephen Ainsworth, Edward C. McGlaughlin
  • Patent number: 9071559
    Abstract: Method and system for configuring a receive packet queue in a network device are provided. The method includes determining how many sub-ports of a port of the network device are configured; assigning memory to each of the configured sub-ports based on the determination of how many sub-ports are configured; determining a flow control scheme to be used for packet transmission; and dividing the receive packet queue based on the determination of the flow control scheme to be used.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: June 30, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Craig M. Verba, Leo J. Slechta, Jr.
  • Patent number: 9069919
    Abstract: A method for providing port arbitration verification for a design under test (DUT) is provided. The method includes sampling the availability of ports at a predetermined number of clock cycles prior to an arbitration point. The method predicts a winner at each of the clock cycles and determines a verification result based on a match between one of the predicted winners and an actual arbitration winner for the DUT.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: June 30, 2015
    Assignee: QLOGIC, Corporation
    Inventor: Philip P. James
  • Patent number: 9049113
    Abstract: Method and systems for a network device are provided. The method includes receiving configuration data having a primitive sequence comprising a first primitive and a second primitive at a first clock rate at a port of the network device; writing the configuration data into a smoothing module of the port at the first clock rate; reading the configuration data out of the smoothing module at a second clock rate; allowing a primitive to be inserted or deleted in the smoothing module to prevent smoothing module underflows or overflow; regenerating the primitive sequence at the second clock rate; and transmitting the regenerated primitive sequence to the destination port.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: June 2, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Ernest G. Kohlwey
  • Patent number: 9047151
    Abstract: Method and system for processing a command received from a processor executable computing entity from among a plurality of computing entities of a computing system that interfaces with a device is provided.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: June 2, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Tanmay Pradip Shete, Jagannatha Narayanaswami, Nilesh Jagannath Lonari, Narender Kumar
  • Patent number: 9047208
    Abstract: Methods and systems for a device are provided. The device includes physical function (PF) representing a physical component and is assigned to an XF group. The XF group includes a plurality of virtual functions (VFs) associated with the PF, each VF identified by a unique number. A number of XF group that are assigned to the PF is configurable depending on the function of the physical component.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: June 2, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Richard S. Moore, Bradley S. Sonksen, Andrew Broughton
  • Patent number: 9046941
    Abstract: Method and system for processing information at a network device connected to a network is provided. The method includes receiving information conforming to a first protocol at a first clock rate at a first sub-port; receiving information conforming to a second protocol at a second clock rate at a second sub-port; storing received information in a temporary storage device at the base-port; reading information out of the temporary storage device at a third clock rate; and processing the information at a MAC module that includes logic that is time-shared among the plurality of sub-ports to process information at the third rate for both the first protocol and the second protocol. The first sub-port is granted access to the logic in a first phase and the second sub-port is granted access to the logic in a second phase for processing the information.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: June 2, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Ernest G. Kohlwey, Lloyd O. Mielke
  • Patent number: 9043519
    Abstract: Method and system for an adapter is provided. The adapter includes a plurality of function hierarchies, with each function hierarchy including a plurality of functions and each function being associated with an event. The adapter also includes a plurality of processors for processing one or more events generated by the plurality of functions. The adapter further includes a first set of arbitration modules, where each arbitration module is associated with a function hierarchy and receives interrupt signals from the functions within the associated function hierarchy and selects one of the interrupt signals. The adapter also includes a second set of arbitration modules, where each arbitration module receives processor specific interrupt signals and selects one of the interrupt signals for processing an event associated with the selected interrupt signal.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: May 26, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Bradley S. Sonksen, Richard S. Moore
  • Patent number: 9003038
    Abstract: Applications executed out of router memory may acquire additional bandwidth that is not being used by other applications, in order to speed up network traffic. Scavenging may occur up to a point where current congestion is detected, at which point any scavenged bandwidth is relinquished and the application returns to its prescribed limit. After current congestion is mitigated, scavenging may occur up to a limit below the point where congestion was detected. After a predetermined interval, additional scavenging may occur beyond this limit until a preset bandwidth limit is reached.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: April 7, 2015
    Assignee: QLOGIC, Corporation
    Inventor: Charles Micalizzi, Jr.
  • Patent number: 8995455
    Abstract: One method includes: (a) providing a memory storage device having a plurality of storage locations for storing information received by a plurality of sub-ports of a base port of the network device, where the memory storage device is shared among the plurality of sub-ports such that each sub-port is given access to the memory storage device at a certain phase of a system clock cycle; (b) storing a packet or a portion thereof at one of the storage locations when a sub-port that receives the packet has access to one or more of the storage locations; and (c) scrambling addresses for the memory storage locations such that a different one of the storage location is available to the sub-port of step (b) for a next write operation in a next phase when the sub-port of step (b) is given access to the memory storage device.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: March 31, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Frank R. Dropps, Craig M. Verba