Abstract: An operation method of a network device and a control chip of the network device are provided. The network device receives an input signal through a fiber medium. The operation method includes the following steps: setting a target speed of the network device to a first speed; transmitting and/or receiving a data at the first speed; and setting the target speed of the network device to a second speed which is different from the first speed when the amplitude or energy of the input signal is not greater than a threshold.

Abstract: A multidrop network system includes N network devices. The N network devices include a master device and multiple slave devices, and each network device has an identification code as its own identification in the multidrop network system. The N network devices have N identification codes and obtain transmission opportunities in turn according to the N identification codes in each round of data transmission. Each network device performs a count operation to generate a current count value, and when the identification code of a network device is the same as the current count value, this network device obtains a transmission opportunity. After a device obtains the transmission opportunity, it determines whether a cut-in signal from another network device is observed in a front duration of a predetermined time slot, and then determines whether to abandon/defer the right to start transmitting in the remaining duration of the predetermined time slot.

Abstract: A chip having a debug function includes functional circuitries, a selector circuitry, a data reconstruction circuitry, and a switching circuitry. Each functional circuitry includes a decoder circuit that stores a corresponding set of debug signals and outputs a corresponding debug signal in the corresponding set of debug signals to be a corresponding signal in first signals according to a corresponding address signal in address signals. The selector circuitry selects second signals from the first signals according to the address signals. The data reconstruction circuitry selects first data from the second signals according to split signals and outputs the same to be debug data. Each first data is partial data of a corresponding signal in the second signals. The switching circuitry determines whether to output the debug data or at least one output signal associated with the functional circuitries via output ports according to switching signals.

Abstract: The present invention discloses a memory test circuit having repair information maintaining mechanism. A repairing control circuit controls a MBISR circuit to perform a self-repair procedure on a memory circuit and includes a remapping storage circuit and a latch storage circuit. The remapping storage circuit receives and stores repairing information generated by the MBISR circuit after the self-repair procedure finishes. The latch storage circuit is electrically coupled between the remapping storage circuit and a remapping circuit corresponding to the memory circuit to receive and store the repairing information from the remapping storage circuit such that the remapping circuit accesses the repairing information therefrom when a scan test is performed on the remapping storage circuit based on a scan chain to perform remapping and repairing on the memory circuit based on the repairing information and a redundant structure of the memory circuit.

Abstract: An amplifier circuit is provided. The amplifier circuit outputs a pair of differential output signals through a first output terminal and a second output terminal. The amplifier circuit includes a first amplifier stage electrically connected to a first node and a second node for amplifying a pair of differential input signals; a second amplifier stage which is electrically connected to the first node and the second node and coupled to the first output terminal and the second output terminal; a first switch, coupled between the first output terminal and a first reference voltage; a second switch, coupled between the second output terminal and the first reference voltage; a third switch, coupled between the first node and the first reference voltage; a fourth switch coupled between the second node and the first reference voltage; and a fifth switch coupled between a second reference voltage and the first amplifier stage.

Abstract: An antenna structure includes a first resonant unit and a second resonant unit. The first resonant unit is configured to transmit an input signal as a first wireless signal. The second resonant unit is configured to transmit the input signal as a second wireless signal. The first resonant unit and the second resonant unit have a substantially identical operating band, and the first resonant unit and the second resonant unit are a single continuous metal structure.

Abstract: A multimedia signal transmission control system is provided, which includes a transmitter control circuit and a receiver control circuit coupled with each other. The transmitter control circuit packs a control signal and at least one of multimedia signals into first hybrid data packets in an active video period of a video frame, and packs the control signal and another at least one of the multimedia signals into second hybrid data packets in a vertical front porch and a vertical back porch of the video frame. The receiver control circuit receives the first hybrid data packets in the active video period, and receives the second hybrid data packets in the vertical front porch and the vertical back porch. The receiver control circuit unpacks the first hybrid data packets and the second hybrid data packets to provide the control signal and the multimedia signals to a display module.

Abstract: A level shifter can achieve a level shift by a wide margin. The level shifter includes a latch circuit, a clamping circuit, a protection circuit, and an input circuit. The latch circuit is coupled between a high-voltage terminal and a pair of output terminals for outputting a pair of output signals. The clamping circuit is coupled between a medium-voltage terminal and the pair of output terminals and limits the minimum voltage of the pair of output signals to the medium voltage. The protection circuit is set between the latch circuit and the input circuit, and prevents an excessive voltage drop between the input circuit and the pair of output terminals. The input circuit includes an input transistor pair coupled between the protection circuit and a low-voltage terminal having a low voltage. The input transistor pair receives a pair of input signals and operates accordingly.

Abstract: An inductor device includes a first trace, a second trace, a first capacitor, and at least one connection element. The first trace includes at least two sub-traces. One terminal of the at least two sub-traces is coupled to a first node. The second trace includes at least two sub-traces. One terminal of the at least two sub-traces is coupled to a second node. The first capacitor is coupled between the first node and the second node. The at least one connection element is coupled to another terminal of the at least two sub-traces of the first trace and another terminal of the at least two sub-traces of the second trace, such that the first trace and the second trace form a closed loop.

Abstract: The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.

Abstract: A character recognition method includes the following operations: determining that the image of character to be identified corresponds to a matching character of several registered characters according to several vector distances to be identified between a vector of an image of character to be identified and several vectors of several registered character images of several registered characters, and storing a matching vector distance between the vector of the image of character to be identified and a vector of the matching character by a processor; and storing a data of the matching character according to the image of character to be identified when the matching vector distance is less than a vector distance threshold by the processor.

Abstract: A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and a resistor. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The second capacitor is coupled between the control terminal of the first switch and the control terminal of the second switch. The resistor is coupled between the control terminal of the second switch and a reference voltage.

Abstract: An inductor device includes an 8-shaped inductor structure, a first spiral wire, a first connector, a second connector, and a first interlaced component. The 8-shaped inductor structure includes two first-wires and two second-wires. The first spiral wire is disposed on an inner side of the two first-wires. The first connector is coupled to one of the two first-wires and one of the two second-wires. The second connector is coupled to another one of the two first-wires. The first interlaced component is coupled to the first spiral wire and another one of the two second-wires, and the first interlaced component is coupled to the first connector and the second connector in an interlaced manner respectively.

Abstract: The present application provides a circuit design method and an associated circuit. The circuit design method is for generating a circuit, and the method includes: arranging a plurality of attack detection circuits around a specific circuit unit, wherein the specific circuit unit is in the circuit; determining a number of a plurality of spare cells required by the circuit according to a number of the attack detection circuit; and placing the spare cells in the circuit according to the number of the spare cells.

Abstract: An integrated inductor is provided. The integrated inductor includes a first winding and a second winding, and has a first end, a second end, and a node. The first winding utilizes the first end and the node as two ends thereof and includes a first coil and a second coil, which do not overlap. The second winding utilizes the second end and the node as two ends thereof and includes a third coil and a fourth coil, which do not overlap. The first coil and the third coil have an overlapping area, and the second coil and the fourth coil have an overlapping area. The first coil is surrounded by the third coil, and the fourth coil is surrounded by the second coil.

Abstract: A processor circuit includes an instruction decode unit, an instruction detector, an address generator and a data buffer. The instruction decode unit is configured to decode a first load instruction included in a plurality of load instructions to generate a first decoding result. The instruction detector, coupled to the instruction decode unit, is configured to detect if the load instructions use a same register. The address generator, coupled to the instruction decode unit, is configured to generate a first address requested by the first load instruction according to the first decoding result. The data buffer is coupled to the instruction detector and the address generator. When the instruction detector detects that the load instructions use the same register, the data buffer is configured to store the first address generated from the address generator, and store data requested by the first load instruction according to the first address.

Abstract: The present application provides a method for a WiFi module and system of the same. The method including: determining whether a specific process is a high-power consumption event; and when the specific process is determined as the high-power consumption event, performing a time-divisional operation upon the specific process. The present application further provides another method for a WiFi module, including: determining whether a specific process is a high-power consumption event; and when the specific process is determined as the high-power consumption event, estimating a first power consumption request information and transmitting the information to a control module of a local end; and receiving a first response corresponding to the first power consumption request information from the control module.

Abstract: An image processing method applied to a display device having a processing circuit and a screen and includes: receiving a first image from one of a plurality of electronic devices; detecting whether the first image has a black border area; and if the first image has the black border area, performing a first display operation, wherein performing the first display operation includes: removing the black border area of the first image, to generate a second image; adjusting the size of the second image according to the size of a display area of the screen; calculating a first blank area of the screen based on the adjusted second image; requesting a third image from another one of the electronic devices according to the size of the first blank area; and filling the display area of the screen with the adjusted second image and the third image.

Abstract: A power supplying circuit includes a first high-voltage switch, a first low-voltage switch, a second high-voltage switch, a second low-voltage switch, and a controller circuit. The first high-voltage switch receives a first input voltage and generates a first node voltage. The first low-voltage switch is coupled between the first high-voltage switch and an output terminal. The second high-voltage switch receives a second input voltage and generates a second node voltage. The second low-voltage switch is coupled between the second high-voltage switch and the output terminal. The controller circuit controls the first high-voltage switch, the first low-voltage switch, the second high-voltage switch, and the second low-voltage switch according to the first node voltage and the second node voltage such that an output voltage is outputted to the output terminal.

Abstract: An inductor device includes a first wire, a second wire, at least one first connector, at least one second connector, and a first center-tapped terminal. The first wire includes a plurality of first sub-wires. The second wire includes a plurality of second sub-wires. The first sub-wires and the second sub-wires are disposed in an interlaced manner. The at least one first connector couples the first sub-wire that is disposed on an outer side and the first sub-wire that is disposed on an inner side in the first sub-wires. The at least one second connector couples the second sub-wire that is disposed on the outer side and the second sub-wire that is disposed on the inner side in the second sub-wires. The first center-tapped terminal is coupled to the first sub-wire that is disposed on the outer side in the first sub-wires.