Abstract: A direct memory access (DMA) controller, an electronic device that uses the DMA controller, and a method of operating the DMA controller are provided. The DMA controller is configured to access a memory that contains a privilege area and a normal area. The method of operating the DMA controller includes the following steps: searching for a DMA channel that is in an idle state in the DMA controller; setting a register value of a mode register of the DMA channel such that the DMA channel operates in a privilege mode; setting a memory address register and a byte count register of the DMA channel; and controlling the DMA channel to transfer data based on the memory address register and the byte count register.

Abstract: An embedded device detection method, comprising the following steps: executing a task by an embedded device, wherein the task comprises multiple functions; when an abnormal interruption occurs to the task, obtaining a stack pointer and a program counter corresponding to the abnormal interruption by a detection device, wherein the program counter is configured to record a memory address in use when the abnormal interruption occurs to the task; obtaining a stack space corresponding to a first target function being executed according to the program counter when the abnormal interruption occurs to the task; finding out a second target function before the first target function is executed according to the stack pointer and the stack space; and correcting the task according to the second target function.

Abstract: A semiconductor structure includes a first inductor, a second inductor, and a first input/output (I/O) pad. The first I/O pad is coupled to the first inductor and the second inductor. The first I/O pad, a first central axis of a first magnetic field of the first inductor, and a second central axis of a second magnetic field of the second inductor are disposed sequentially along a first direction.

Abstract: The present invention discloses a receive data equalization apparatus. A delay-compensating calculation circuit retrieves training data groups of a training data signal to retrieve total delay amount, generate signed compensation amounts according to a relation among training data contents of training data in each of the training data groups to generate total compensation amount accordingly, and solve equations that correspond total delay amount of the training data groups to the total compensation amount to obtain each of the compensation amounts. A receive data equalization circuit receives the compensation amounts and retrieves a receive data group in a receive data signal, generate signed receive compensation amounts according to a relation among receive data contents of receive data in the receive data group to generate a total receive compensation amount accordingly to perform equalization on a terminal edge of the receive data group according to the total receive compensation amount.

Abstract: A transmitter includes a pre-driver stage circuitry, a post-driver stage circuitry, and resistance adjustment circuits. The pre-driver stage circuitry is configured to output a second data signal according to a first data signal. The post-driver stage circuitry is configured to output a third data signal according to the second data signal. The resistance adjustment circuits are configured to provide a first variable resistor and a second variable resistor, and transmit a first power supply voltage and a second power supply voltage to at least one of the pre-driver stage circuitry or the post-driver stage circuitry, in order to adjust a slew rate of the third data signal.

Abstract: A convolution time de-interleaver includes an input buffer, an output buffer, a memory, an input control circuit, an output control circuit, and a controller. The memory includes a plurality of memory blocks. The input control circuit sequentially outputs a plurality of entries of data to a plurality of input register unit groups of the input buffer respectively and correspondingly. After a predetermined amount of data have been written to the input buffer, the controller writes part of data stored in the input buffer to a corresponding memory block. After the plurality of memory blocks are written, the controller writes data stored in a corresponding memory block to the output buffer. The output control circuit sequentially outputs a plurality of pieces of data stored in a plurality of output register unit groups of the output buffer.

Abstract: A semiconductor capacitor array layout includes a first conductive structure and a second conductive structure. The first conductive structure includes: longitudinal first conductive strips in a first integrated circuit (IC) layer; and lateral first conductive strips that are in a second IC layer and coupled to the longitudinal first conductive strips. The longitudinal and lateral first conductive strips jointly form well-shaped structures including outer wells and inner wells. The outer wells are not electrically coupled to the inner wells. The second conductive structure includes second conductors that are respectively disposed in the well-shaped structures in the first IC layer. The second conductors include outer second conductors respectively positioned in the outer wells and inner second conductors respectively positioned in the inner wells. The outer second conductor are not electrically coupled to the inner second conductor.

Abstract: An audio and video transmission system includes a multimedia device. The multimedia device includes a high-definition multimedia interface (HDMI) receiver, a first transfer circuit, and a first universal serial bus type C (USB-C) interface. The first transfer circuit is configured to transfer a first audio signal output by an audio channel pin of the HDMI receiver into a second audio signal in a universal serial bus (USB) interface format. The first USB-C interface is configured to transmit the second audio signal. The HDMI audio channel pin is an audio return channel (ARC) pin or an enhanced ARC pin.

Abstract: A cable includes a first plug, a second plug, and a controller. The first plug is configured to be connected with a host. The second plug is configured to be connected with a device. The controller is coupled between the first plug and the second plug, and is configured to monitor a connection message transferred between the host and the device, and to determine, according to the connection message, a transfer mode that the host and the device is to enter, and to set a plurality of electrical parameters to be a corresponding one set in a plurality of sets of predetermined parameters.

Abstract: A direct memory access (DMA) controller, an electronic device that uses the DMA controller, and a method of operating the DMA controller are provided. The DMA controller is configured to access a memory that contains a secure area and a non-secure area. The method of operating the DMA controller includes the following steps: searching for a DMA channel that is in an idle state in the DMA controller; setting a register value of a mode register of the DMA channel such that the DMA channel operates in a secure mode; setting a memory address register and a byte count register of the DMA channel; and controlling the DMA channel to transfer data based on the memory address register and the byte count register.

Abstract: An inductor device includes an 8-shaped inductor and a ring-type wire. The ring-type wire is disposed around an outer side of the 8-shaped inductor. The 8-shaped inductor includes an input terminal and a center-tapped terminal. The input terminal of the 8-shaped inductor is located on a first side of the inductor device, and the center-tapped terminal is located on a second side of the inductor device. The ring-type wire includes an input terminal and a ground terminal. The input terminal of the ring-type wire is located on the first side of the inductor device, and the ground terminal is located on the second side of the inductor device. The input terminal of the ring-type wire is coupled to the input terminal of the 8-shaped inductor.

Abstract: A double 8-shaped inductive device includes a first 8-shaped coil, a second 8-shaped coil, and a connection structure. The first 8-shaped coil includes a first connecting terminal. The second 8-shaped coil includes a second connecting terminal, which the first 8-shaped coil and the second 8-shaped coil are to be disposed side by side on two sides of a first imaginary line. The connection structure electrically couples to the first connecting terminal and the second connecting terminal, such that the first 8-shaped coil and the second 8-shaped coil form a connected circuit, and the first 8-shaped coil and the second 8-shaped coil include a loop respectively.

Abstract: An output buffer set is coupled to a first pair of pins and configured to output art audio output signal to the first pair of pins. A direct current (DC) shifting buffer set is coupled between the audio codec circuit and the first pair of pins, and is directly coupled to the output buffer set and the first pair of pins. An audio port is coupled to the first pair of pins. The DC shifting buffer set is configured to receive a first audio input signal from the audio port through the first pair of pins. The audio codec circuit is configured to record the audio output signal back and mix the recorded audio output signal with a second audio input signal, or mix the first audio input signal with a third audio input signal.

Abstract: Inductor device includes first and a second coils. First coil is wound into plural first circles. Second coil is wound into plural second circles. First connection member is coupled to first circle between outermost and innermost sides among first circles located at first area and first circle on outermost side among first circles located at second area. Second connection member is coupled to second circle on outermost side among second circles located at first area and second circle between outermost and innermost sides among second circles located at second area. At least two first circles of first circles are located at first area, and half of first circle of first circles is located at second area. Half of second circle of second circles is located at first area, and at least two second circles of second circles are located at second area.

Abstract: A transformer device includes a first coil and a second coil. The first coil includes a number of first circles. The second coil includes a number of second circles. A first side of a first one of the first coil is adjacent to one of the first coil, and a second side of the first one of the first coil is adjacent to one of the second coil. A first side and a second side of a second one of the first coil are adjacent to one of the second coil, respectively.

Abstract: A time-division multiplexing (TDM) scheduler determines a service order for serving N packet transmission requesters. The TDM scheduler includes: N current count value generators configured to serve the N packet transmission requesters respectively, and generate N current count values according to parameters of the N packet transmission requesters, a previous scheduling result generated by the EDD scheduler previously, and a predetermined counting rule; and an earliest due date (EDD) scheduler configured to generate a current scheduling result for determining the service order according to the N current count values and a predetermined urgency decision rule, wherein an extremum of the N current count values relates to one of the N packet transmission requesters, and the EDD scheduler selects this requester as the one to be served preferentially.

Abstract: A shielding structure is disclosed. The shielding structure includes a patterned shielding layer and a ring structure. The patterned shielding layer is extended along a plane and located between an inductor structure and a substrate. The ring structure is coupled to and stacked on the patterned shielding layer along a first direction. The first direction is perpendicular to the plane. The ring structure surrounds the patterned shielding layer. The ring structure includes at least one opening and a ground terminal.

Abstract: An electronic device includes a temporary memory, a non-volatile memory and a processor. The temporary memory includes at least one secure region. The non-volatile memory is configured to store at least one higher-level secure program and a plurality of commands. The processor is connected to the temporary memory and the non-volatile memory for executing the plurality of commands to: when receiving a wake-up command, initialize the at least one secure region; and through the at least one higher-level secure program, recover the at least one secure region, or decrypt encrypted data stored in the non-volatile memory to recover the at least one secure region. In addition, a hibernation recovery method is also disclosed herein.

Abstract: The present disclosure discloses a memory access interface device. A data processing circuit receives a data signal including 2M pieces of data from a memory device. A sampling clock generation circuit receives a data strobe signal from the memory device to generate a valid data strobe signal having P valid strobe pulses and further generate a sampling clock signal accordingly, in which P is larger than M. A sampling circuit samples the data signal according to the sampling clock signal to generate sampling results. A control circuit determines valid sampling results according to a time difference between the valid data strobe signal and the data signal and outputs valid data generated according to the valid sampling results as a read data signal to a memory access controller.

Abstract: An electrostatic discharge (ESD) protection circuit is provided, which includes multiple ESD clamping circuits and a shunt circuit. The multiple clamping circuits comprise multiple transistors, respectively. The multiple transistors are coupled in series between a first power line and a second power line. A shunt circuit is coupled with a first terminal and a control terminal of a first transistor of the multiple transistors. The shunt circuit is configured to conduct the first terminal of the first transistor to the control terminal of the first transistor during a period of an ESD event to raise a voltage of the control terminal of the first transistor. The shunt circuit insulates the first terminal of the first transistor from the control terminal of the first transistor during a period outside the period of the ESD event.