Abstract: A processor circuit sends a read request. A clock signal of the processor circuit corresponds to a first counting value. A memory circuit stores data and sends a data strobe signal in response to the read request. The data strobe signal corresponds to a second counting value. The processor circuit includes a selector circuit and a feedback circuit. The selector circuit selects and outputs a flag signal from a plurality of flag control signals according to the second counting value. The feedback circuit generates an enable signal according to a set signal associated with the first counting value, the flag signal associated with the second counting value, and a data strobe gate signal, and generates the data strobe gate signal according to the enable signal and the data strobe signal. The processor circuit reads the data according to the data strobe gate signal.

Abstract: Disclosed is a graphics processing device including a main SoC, a performance-enhancing SoC, and an external circuit that is set outside any of the two SoCs. The main SoC includes: a first graphics processing unit (GPU) dividing to-be-processed data into a first input part and a second input part, and processing the first output part to generate first output data; and a first transceiver circuit forwarding the second input part to the performance-enhancing SoC via the external circuit, and then receiving second output data via the external circuit and forwarding it. The performance-enhancing SoC includes: a second transceiver circuit receiving the second input part via the external circuit and outputting the second output data to the main SoC via the external circuit; and a second GPU receiving the second input part from the second transceiver circuit and processing this part to provide the second output data for the second transceiver.

Abstract: A semiconductor capacitor array layout generates parasitic capacitance toward an edge of the layout so as to reduce a capacitance difference between an outer capacitor unit and an inner capacitor unit. The semiconductor capacitor array layout includes a first conductive structure and a second conductive structure. The first conductive structure includes: longitudinal first conductive strips disposed in a first integrated circuit (IC) layer; and lateral first conductive strips disposed in a second IC layer. The longitudinal and lateral first conductive strips jointly form well-type structures including outer wells and inner wells that are electrically connected. The second conductive structure includes second conductors disposed in the first IC layer. The second conductors include outer conductors and inner conductors that are electrically disconnected and respectively disposed in the outer wells and the inner wells. The outer wells and the closest inner conductors jointly generate parasitic capacitance.

Abstract: A latency adjustment method includes the following operations: in response to a predetermined event of a data stream occurred during a first interval, performing a transmission status determining operation to determine whether a transmission status of the data stream is stable; in response the transmission status being stable, determining whether a total number of times of packet loss compensation events of the data stream occurred during a previous interval is higher than a first predetermined value; and in response to the transmission status being unstable or the total number of times being higher than the first predetermined value, increasing a latency of the data stream.

Abstract: A charge-steering amplifier circuit and a control method thereof are provided. The charge-steering amplifier circuit is used for amplifying a differential input signal and includes a sample-and-hold circuit, a charge-steering amplifier, a reference voltage generation circuit, and a switch circuit. The sample-and-hold circuit is configured to sample the differential input signal to generate first and second sampled signals. The charge-steering amplifier has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first and second input terminals receive the first and second sampled signals, respectively. The reference voltage generation circuit is configured to generate a reference voltage according to the differential input signal. The switch circuit is configured to couple the reference voltage to the first output terminal and the second output terminal.

Abstract: An audio processing device includes a signal processing circuit, a power switch circuit, a power amplifier and a detection circuit. The signal processing circuit is configured to process an audio input to generate an audio signal. The power switch circuit is configured to generate an operating voltage. The power amplifier is coupled with the signal processing circuit and the power switch circuit, and configured to drive a load circuit by the operating voltage according to the audio signal. The detection circuit is coupled with the signal processing circuit and the power switch circuit, configured to obtain a volume value from the audio signal and compare the volume value with a first volume threshold to generate a comparison result, and configured to control, according to the comparison result, the power switch circuit to set the operating voltage to have a corresponding one of multiple voltage levels.

Abstract: A dynamic element method includes the following operations: summing up most significant bits of a digital code in a previous period and a pointer signal in the previous period, in order to generate a first signal; outputting the first signal to be an adjusted pointer signal according to a clock signal; and decoding the adjusted pointer signal to be control signals, in which the control signals are configured to set corresponding relations of components of a first digital to analog converter circuits and the most significant bits, in order to utilize the components to convert the most significant bits.

Abstract: The application discloses a method, for building an oscillator frequency adjustment lookup table in a transceiver, wherein the transceiver generates a clock according to a crystal oscillator external to the transceiver for transceiving data. The transceiver includes adjustable capacitor arrays assembly connected to the crystal oscillator, wherein when an equivalent capacitance of the adjustable capacitor assembly is a reference value, the crystal oscillator has a reference frequency, and when the equivalent capacitance changes relative to the reference value, the crystal oscillator correspondingly has a frequency offset relative to the reference frequency. The method includes: performing an interpolation operation according to a first value, a second value, and a third value of the equivalent capacitance, and the corresponding frequency variations, so as to obtain the frequency variations corresponding to a first sub-value between the first value and the second values.

Abstract: A multimedia audio/video system includes a multimedia audio/video transmitting end and a multimedia audio/video receiving end. The multimedia audio/video transmitting end includes a multimedia data generator and a first data converter. The multimedia data generator is used to generate a multimedia data conforming to a first transmission protocol. The first data converter is used to convert the multimedia data conforming to the first transmission protocol into a multimedia data conforming to a second transmission protocol. The multimedia audio/video receiving end includes a second data converter which is used to convert the multimedia data conforming to the second transmission protocol into the multimedia data conforming to the first transmission protocol. The multimedia data conforming to the first transmission protocol is transmitted via multiple cables, while the multimedia data conforming to the second transmission protocol is transmitted via a single cable.

Abstract: A scan test device includes a scan flip flop circuit and a clock gating circuit. The scan flip flop circuit is configured to receive a scan input signal according to a scan clock signal, and to output the received scan input signal to be a test signal. The clock gating circuit is configured to selectively mask the scan clock signal according to a predetermined bit of the test signal and a scan enable signal, in order to generate a test clock signal for testing at least one core circuit.

Abstract: An audio signal processing circuit includes a filter, a gain control circuit, and a bass boost circuit. The filter filters an audio signal and produces a filtered signal accordingly. The gain control circuit divides the filtered signal in the time domain into a first segment and a second segment that are substantially equal in length, measures a first amplitude of the first segment and a second amplitude of the second segment, and generates a gain based on the first amplitude which is greater than the second amplitude. The bass boost circuit adjusts the amplitudes of the first segment and the second segment according to the gain.

Abstract: The present disclosure discloses a video interface conversion device that includes a first and a second interface transmission circuit, a color conversion circuit and an image compression circuit. The first and the second interface transmission circuit are respectively electrically coupled to an image source and a display terminal. The second interface transmission circuit negotiates a maximum output bandwidth with the display terminal such that the first interface transmission circuit compares an input data bandwidth of a data signal received from the image source and the maximum output bandwidth. When the maximum output bandwidth is smaller than the input data bandwidth, an image compression and/or a color coding conversion is performed on the data signal, and the data signal having the processed input data bandwidth being smaller than or equal to the maximum output bandwidth is further transmitted by the second interface transmission circuit to the display terminal.

Abstract: A successive approximation register analog to digital converter includes a sampling circuitry, a comparator circuit, and a controller circuitry. The sampling circuitry generates first and second signals according to a sampled signal. The comparator circuit compares the first signal with the second signal to generate first decision signals. The controller circuitry generates digital codes according to the first decision signals, and controls the comparator circuit to perform comparisons repeatedly to generate second decision signals, in order to generate a digital output according to the digital codes, a statistical noise value, and the second decision signals.

Abstract: The present invention discloses a DAC method having signal calibration mechanism. A first conversion circuit generates a first analog signal according to an input digital signal. A second conversion circuit generates a second analog signal according to the input digital signal and a pseudo-noise digital signal. An echo transmission circuit processes a signal on an echo path to generate an echo signal. A first and a second calibration circuits generate a first and a second calibration signals. A calibration parameter calculation circuit performs calculation according to a difference between the echo signal and a sum of the first and the second calibration signals and related path information to generate a first and a second offsets. The first and the second calibration circuits converge first and second response coefficients and update a first and a second codeword offset tables according to the first and the second offsets.

Abstract: The present invention discloses a printed dual band antenna that includes a primary radiation portion and a parasitic radiation portion. The primary radiation portion is configured to perform signal transmitting and receiving based on a first resonant frequency and a second resonant frequency. The parasitic radiation portion is disposed on a neighboring side of the primary radiation portion, distanced from the primary radiation portion by a distance and electrically isolated from the primary radiation portion. The parasitic radiation portion couples to and resonates with the primary radiation portion to perform signal transmitting and receiving based on the second resonant frequency. The parasitic radiation portion is a grounded monopole parasitic antenna.

Abstract: An inductor device includes a first inductor and a second inductor. The first inductor has a first winding and a second winding. The second inductor has a third winding and a fourth winding, and the second inductor is disposed adjacent to the first inductor, and the second inductor is coupled to the first inductor in an interlaced manner.

Abstract: The present invention discloses an isolation circuit having test mechanism. An isolation circuit component performs signal transmission when a signal that a control terminal receives has an enabling state and performs signal isolation when the signal has a disabling state. The test circuit includes a multiplexer and a control circuit. Under a shifting operation state in a test mode, the control circuit controls the multiplexer to select an operation input terminal to receive and output an isolation control signal having the enabling state to the control input terminal. Under a capturing operation state in the test mode, the control circuit controls the multiplexer to select a test input terminal to receive and output the test signal to the control input terminal. The control circuit further determines whether the isolation circuit performs signal transmission or signal isolation according to the signals at the data input terminal and the data output terminal.

Abstract: A test circuit for testing a memory is provided. The input of the memory is coupled to a register, and the register is coupled to a logic circuit. The test circuit includes a first test register group, a second test register group, a first multiplexer, and multiple second multiplexers. The first test register group includes at least one test register. The second test register group includes at least one test register. The first multiplexer is coupled between the first test register group and the register. The second multiplexers are coupled between the second test register group and the register.

Abstract: A power supply management device includes an internal power supply circuit, switches, a comparator circuit, and a control circuit. The internal power supply circuit is configured to output a first supply voltage to a node. The switches are coupled between the node and a plurality of first circuits. The comparator circuit is configured to compare a voltage on the node with a reference voltage when the node does not receive the first supply voltage to generate a flag signal. The control circuit is configured to determine whether the node receives a second supply voltage from an external power supply circuit according to the flag signal. If the node receives the second supply voltage, the control circuit is further configured to turn off the internal power supply circuit and gradually turn on the switches, in order to provide the second supply voltage to the first circuits via the switches.

Abstract: Disclosed is a sorting device configured to sort N numbers with N rounds of sorting processes from a first round sorting process to an Nth round sorting process and obtain N-rounds sort results from a first-round sort result to an Nth-round sort result, wherein at least two pairs of numbers of the N numbers are sorted in each of the N rounds of sorting processes concurrently, a Kth-round sort result is dependent on a (K?1)th-round sort result, the Nth-round sort result is the N numbers in a descending/ascending order, and the N is an integer greater than two. The sorting device includes sorting circuits and duplicating circuits that are selectively used for each of the N rounds of sorting processes. Each sorting circuit is configured to sort two numbers and obtain the collating sequence of the two numbers. Each duplicating circuit is configured to output a number it received.