Abstract: A storage device may utilize a host memory buffer for re-ordering commands in a submission queue. Out of order commands in a submission queue that uses host virtual buffers that are not the same size may be difficult to search. Accordingly, commands in a submission queue may be correctly ordered in a host memory buffer before being put into the host virtual buffers. When the commands are in order, the search operation for specific data is improved.

Abstract: A data storage device includes a memory and a controller. The memory includes a first partition and a second partition. The controller includes a pattern detector that is configured to detect one or more tags in data from an access device to be stored in the first partition. The controller is configured to generate, in the second partition, one or more links to the data that is stored in the first partition, the one or more links organized according to metadata associated with the one or more tags.

Abstract: Apparatuses, systems, and methods are disclosed for offset trimming for differential amplifiers. An apparatus includes a differential amplifier. A differential amplifier includes a non-inverting input, an inverting input, and an output coupled to the inverting input via a voltage divider. A first variable current source is coupled to a non-inverting input, so that increasing a current from the first variable current source increases a voltage at the non-inverting input. A second variable current source is coupled to an inverting input, and to an output via a voltage divider, so that increasing a current from the second variable current source decreases a voltage at the output.

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to maintain a first address translation table associated with the memory and a second address translation table associated with the memory. The controller is further configured to receive a command to erase the memory. The controller is further configured to switch an indicator of an active address translation table from the first address translation table to the second address translation table in response to receiving the command.

Abstract: A data storage device includes a controller and a memory die. The controller includes a host interface and a memory interface. A method includes receiving a message from a host device via the host interface. The message indicates that the host device is to perform a first adjustment process associated with the host interface. The method further includes performing a second adjustment process associated with the memory interface in response to receiving the message indicating that the host device is to perform the first adjustment process.

Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.

Abstract: A memory system includes blocks (or other groupings) of memory cells including data memory cells and dummy memory cells. In order to mitigate program disturb or other issues, the memory system applies a gate voltage based on temperature to all or a subset of the dummy memory cells as part of a memory operation.

Abstract: A system for using bad blocks in a memory system is proposed. The system includes accessing an identification of a plurality of bad blocks and corresponding error codes which, for example, were generated during a manufacturing test and stored on the memory integrated circuit. The system determines which blocks of the plurality of bad blocks to test for being still usable and which blocks of the plurality of bad blocks not to test for being still usable based on corresponding error codes. For each bad block that should be tested, a test from a plurality of tests is chosen based on the corresponding error code in order to determine if the bad block is still usable. Those blocks determined to be still usable are subsequently used to store non-mission critical information.

Abstract: A storage system and method for improved command flow are provided. In one embodiment, a storage system receives a request from a host for an indication of which command(s) stored in the storage system are ready for execution; in response to the request, provides the host with the indication of which command(s) stored in the storage system are ready for execution; receives an instruction from the host to execute a command that is ready for execution; and in response to the instruction from the host to execute the command, performs both of the following: executes the command and provides the host with an updated indication of which command(s) stored in the storage system are ready for execution, wherein the storage system provides the host with the updated indication without receiving a separate request from the host for the updated indication. Other embodiments are provided.

Abstract: Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.

Abstract: A storage system and method for recovering data corrupted in a host memory buffer are provided. In one embodiment, a storage system is provided comprising a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to receive a logical-to-physical map from a volatile memory of a host for storage in the storage system's non-volatile memory; determine if there is an error in an entry in the logical-to-physical map; in response to determining that there is no error in the logical-to-physical map, store the logical-to-physical map in the non-volatile memory; and in response to determining that there is an error in an entry in the logical-to-physical map, attempt to recover the entry from a location in the storage system before storing the logical-to-physical map in the non-volatile memory. Other embodiments are provided.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage (Vth) of a memory cell can shift depending on when the read operation occurs. In one aspect, a dummy voltage is applied to the word lines to cause a coupling up of the word lines and weak programming. This can occur when a specified amount of time has elapsed since a last program or read operation, or when a power on event is detected for the memory device. A number of read errors can also be considered. The dummy voltage is similar to a pass voltage of a program or read operation but no sensing is performed. The word line voltages are therefore provided at a consistently up-coupled level so that read operations are consistent. The coupling up occurs due to capacitive coupling between the word line and the channel.

Abstract: A storage device with a memory may implement command throttling in order to control power usage. The throttling may be based on modifications of certain memory parameters, such as a reduction in clock rate, bus speed, operating voltage, or command type changes. The throttling may be performed at a back end or memory interface of the storage device such that the memory interface receives un-throttled commands and can optimally throttle all of the commands from the front end.

Abstract: Methods and systems for managing data storage in a non-volatile memory system are disclosed. The method may include receiving data, determining a data classification for the received data from a predetermined plurality of data classifications, writing the received data to an open block having only data of a same data classification as the determined data classification and, upon completely programming the open block, associating an epoch indicator where the epoch indicator defines a time period within which the block was created. When a block reclaim trigger is detected, only data within a same data classification and epoch may be reclaimed. An incrementing epoch indicator identifies a predetermined time granularity and is assigned to data such that earlier data and newer data are distinguishable. A system to implement the method may include a non-volatile memory and a controller configured to track and apply epoch and data-type classification information for data.

Abstract: A method is provided that includes providing a memory device including a first word line, a vertical bit line, a non-volatile memory material disposed between the first word line and the vertical bit line, and a memory cell disposed between the first word line and the vertical bit line. The first word line has a first height. The method further includes forming one or more conductive filaments in the memory cell. The one or more conductive filaments are substantially confined to a filament region having a second height less than the first height and disposed substantially about a vertical center of the memory cell.

Abstract: A storage device may utilize a host memory buffer for re-ordering commands in a submission queue. Out of order commands in a submission queue that uses host virtual buffers that are not the same size may be difficult to search. Accordingly, commands in a submission queue may be correctly ordered in a host memory buffer before being put into the host virtual buffers. When the commands are in order, the search operation for specific data is improved.

Abstract: Systems and methods for detecting program disturb and for programming/reading based on the detected program disturb are disclosed. Program disturb comprises unintentionally programming an unselected section of memory during the program operation of the selected section of memory. To reduce the effect of program disturb, the section of memory is analyzed in a predetermined state (such as the erase state) for program disturb. In response to identifying signs of program disturb, the voltages used to program the section of memory (such as the program verify levels for programming data into the cells of the section of memory) may be adjusted. Likewise, when reading data from the section of memory, the read voltages may be adjusted based on the adjusted voltages used for programming. In this way, using the adjusted programming and reading voltages, the effect of program disturb may be reduced.

Abstract: A system and method for compacting data in a non-volatile memory system that may reduce the need for control data updates is described. The method may include copying valid data from a source block to a destination block, and also writing new host data to the destination block, such that the offset position in the destination block of the copied data is the same as in the source block and fewer mapping table updates are needed for the copied data. The system may include a non-volatile memory system with a coarse granularity mapping table and a fine granularity mapping table where a controller in the non-volatile memory system is configured to only update the coarse granularity mapping table for compacted data written to a new block, but is configured to update both the fine and coarse granularity mapping tables for new host data written to the new block.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for data register copying for a non-volatile storage array. An apparatus may include an array of non-volatile storage cells. A set of write buffer data registers may be configured to store target data for a program operation for an array. Write buffer data registers may communicate target data to corresponding columns of an array. A set of shadow data registers may be configured to receive target data from peripheral circuitry for an array. A portion of target data received by a shadow data register may be copied to a corresponding write buffer data register while the shadow data register receives the portion of the target data.

Abstract: A voltage regulator circuit is provided in which voltage overshoots are quickly dissipated using a discharge path which is connected to an output of the voltage regulator. Circuitry for controlling the discharge path is provided using internal currents of an error amplifier to provide a space-efficient and power-efficient design with a fast response. Moreover, hysteresis can be provided to avoid toggling between discharge and no discharge, and to avoid undershoot when discharging the output. A digital or analog signal is set which turns the discharge transistor on or off. A current pulldown may be arranged in the discharge path.