Abstract: Apparatus and method for determining when to save values of read counters are disclosed. Read counters store values that indicate the number of reads in respective blocks of a memory device. The values of the read counters may be stored in volatile memory, and may be periodically stored to non-volatile memory. The frequency at which the values of the read counters are stored to non-volatile memory may be dependent on the read disturb effect. One measure of the read disturb effect may be based on the characteristics of the respective blocks of the memory device, such as whether the respective block is open/closed, has on-chip copy, and whether the read is to a boundary wordline.

Abstract: A storage device and method for detecting and handling burst operations are provided. In one embodiment, a method for operating a storage device in burst mode is provided. The storage device senses a change in behavior of a host in communication with the storage device, determines whether the sensed change in behavior of the host is indicative of the host's need for the storage device to operate in burst mode by comparing the sensed change in behavior with prior changes in behavior that triggered prior burst modes in the storage device, and in response to determining that the sensed change in behavior of the host is indicative of the host's need for the storage device to operate in burst mode, operates the storage device in burst mode. Other embodiments are provided.

Abstract: A non-volatile memory system may include a controller configured for parsing a host file system, identifying a location of a host file system directory and tracking directory entries of files deleted from the host file system directory but having valid data mappings in the logical-to-physical mapping table. The controller may then store the location of the host file system directory, monitor activity in the host file system directory and track validity status information for use in optimizing a compaction process. The compaction process may include segregating into separate compaction destination blocks valid data based on the stored validity status such that data valid in both the host file system directory and the logical-to-physical mapping table is in compaction destination blocks separate from data having valid logical-to-physical mapping entries but associated with deleted host file system directory entries.

Abstract: A memory system and method are provided for performing garbage collection on blocks based on their obsolescence patterns. In one embodiment, a controller of a memory system classifies each of the plurality of blocks based on its obsolescence pattern and performs garbage collection only on blocks classified with similar obsolescence patterns. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A memory system and method for reducing peak current consumption. In one embodiment, a method is provided that is performed in a memory system comprising a memory with a plurality of blocks, wherein each block has a peak current consumption. In this method, a plurality of metablocks is created, wherein each metablock is created by grouping together blocks with complementary peak current consumption. Next, the metablocks are programmed. Because each of the metablocks has blocks with complementary peak current consumption, each of the metablocks has similar peak current consumption when programmed. Other embodiments are provided.

Abstract: A storage device with a memory may include improved endurance and programming speed by modifying the programming states of the memory blocks. For example, the blocks may be three bit memory blocks, but a dynamic reassignment of verify levels and read margins can result in the block acting like a two bit memory block. Memory blocks may be designed for a certain number of bits per cell (i.e. number of states) and the programming is based on that number. However, single level cell (SLC) programming is still possible in addition to programming according to the number of bits per cell that the memory is designed for. Multiple SLC programming steps can be used to modify the number of states for certain memory cells by the memory controller.

Abstract: A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench includes a first top surface, and a second top surface. A difference between a height of the second top surface and a height of the first top surface is less than a predetermined value ?MAX.

Abstract: A temperature identification system may include temperature sensing circuitry and a temperature measurement module. The temperature sensing circuitry may include a ring oscillator that generates a ring oscillator output signal having a frequency that varies depending on an operating temperature on the ring oscillator. A frequency divider circuit may divide the frequency of the ring oscillator output signal such that two or more cycles of a noise component of supply voltage are averaged, which may reduce the impact that the noise has on the frequency of the ring oscillator output signal. In some embodiments, a regulator may supply a regulated voltage to the ring oscillator. The regulator may reduce the impact of the noise for low frequency components of the noise, while the frequency divider may reduce the impact for high frequency of the noise.

Abstract: A memory system and method are provided for generating a seed value. In one embodiment, a memory system identifies a random defect in a memory die and, in accordance with the identified random defect in the memory die, generates a seed value, wherein with the generated seed value a random number can be generated. Other embodiments are provided, which can be used alone or in combination with one another.

Abstract: A storage device with a memory may improve yield by reducing the allocation of blocks for secondary writes in a dual programming system. In a dual programming system, all host writes are written to both a primary copy and to a secondary copy. If the secondary copy blocks that are available have a higher endurance, then the overall allocation of available blocks for use as a secondary copy block can be reduced (improving yield). In one embodiment, utilizing different trim parameters for the secondary copy blocks may be used to increase the endurance for those blocks. Before programming the secondary copy, the trim parameters may be adjusted to increase endurance and after programming the secondary copy, the trim parameters may be adjusted back to the default value that is used when programming the primary copy.

Abstract: A cluster association recognition system and related method are described. The system may identify sequences of data clusters in compilations of cluster journals. The system may generate the compilations by populating the cluster journals with cluster identifications associated with host addresses identified in host read requests. Upon receipt of future read requests, the cluster sequences may be used to identify data sets that are associated with a cluster sequence in order to identify further data sets that a host is likely to request.

Abstract: A non-volatile memory system may include a non-volatile memory die storing a requested data set that a host requests to be read. In response to the host request, a copy of a data set may be retrieved from the non-volatile memory die without performing error correction on an entry identifying a physical address where the data set is stored. If the data set copy matches the requested data set, the data set copy may be sent to the host. If the data set copy does not match the requested data set, then error correction may be performed on a copy of the entry to identify the correct physical address where the requested data set is stored. A copy of the requested data set may then be retrieved and sent to the host.

Abstract: A memory system and method are provided for adaptive auto-sleep and background operations. In one embodiment, a controller of a memory system measures an amount of time between when the memory completes an operation and when the controller receives a command to perform another operation in the memory. The controller adjusts a time period after which the controller enters an auto-sleep mode and/or starts a background operation based on the measured amount of time. Other embodiments are disclosed.

Abstract: Methods and systems for generating voltages greater than a supply voltage are described. A charge pump system may generate a boosted output voltage greater than the supply voltage using one or more charge pump stages that are arranged in series between the supply voltage and the boosted output voltage. The charge pump system may include clock freezing circuitry that eliminates glitches in clock signals used for driving the one or more charge pump stages. In one example, the clock freezing circuitry may freeze a clock signal that drives a charge pump stage (i.e., prevent the clock signal from switching) when a feedback flag of the charge pump system is in a disable state (e.g., is low). When the feedback flag is in an enable state (e.g., is high), then the clock signal may toggle between a high state and a low state.

Abstract: The apparatus to transfer heat from memory components includes a first non-volatile memory component and a second non-volatile memory component. The apparatus includes a heat spreading material in thermal communication with the first non-volatile memory component and the second non-volatile memory component. The heat spreading material is configured to transfer heat from the first non-volatile memory component and the second non-volatile memory component.

Abstract: A reticle for a semiconductor lithography process includes a glass plate having regions with a reduced optical transmission factor. The regions may include arrays of elements comprising defects such as cracks or voids which are formed by laser pulses. The regions may be adjacent to openings in an opaque material at the bottom of the reticle to shield the openings from a portion of the light which illuminates the reticle from the top. As a result, the light which exits the reticle and is used to pattern a substrate has an asymmetric intensity. This allows the substrate to be patterned with an inspection mark which indicates whether a defocus condition exists, and whether there is a positive or negative defocus condition. Related methods use a reticle to form a pattern on a substrate and for adjusting a focus condition using a reticle.

Abstract: A memory system and method for power management are disclosed. In one embodiment, a memory system maintains a variable credit value indicating an amount of power currently available for memory operations in the memory system, the variable credit value having an upper limit that reflects a maximum power limit for the memory system. The memory system receives a command to perform a memory operation, wherein a plurality of resources are required to perform the memory operation, each resource being associated with a credit value. Prior to performing the memory operation, the memory system checks whether the variable credit value indicates that there is sufficient power available to perform the memory operation. Resource(s) required to perform the memory operation that are already being used in the memory system are not counted against the variable credit value.

Abstract: Systems and methods for reducing sensing time for sensing data states stored within a plurality of memory cells are described. In some cases, the ramping of a word line connected to the plurality of memory cells may be delayed until a threshold current corresponding with a particular number of erased memory cells of the plurality of memory cells has been met or exceeded. The threshold current may be compared with a summation of a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells that have been sensed to be in a conducting state while the word line is set to a voltage level for sensing erased memory cells. The threshold current may be set based on a chip temperature and/or a particular number of bit errors that occurred during a prior sensing operation.

Abstract: Methods and systems for sensing memory cells using a sense amplifier that can support both ramp sensing and conventional sensing are described. With ramp sensing, a word line of a memory array may be ramped up linearly and a sensing operation may be performed by the sense amplifier while the word line is continuously being ramped up. In this case, during the sensing operation, the sense amplifier may sense a bit line of the memory array connected to a memory cell while the word line is ramping up and then transfer the result into a data latch. In contrast, with conventional sensing, a bit line of the memory array may be first precharged to a particular voltage level (e.g., a read voltage level) and then sensed while the word line is held at the particular voltage level.

Abstract: A storage device with a memory may include memory block leveling that improves data retention by considering localized temperature. A block's distance from a heat source may result in variance of data retention. The localized temperature may be used to improve data retention through a relocation, refreshing, or leveling of blocks that considers their physical location on the die and/or in the package.