Abstract: Methods and systems for verifying two or more programming states at the same time are described. During a program verify operation, two or more memory cell threshold voltage levels may be concurrently verified by applying a word line voltage to a plurality of memory cells, applying two or more different bit line voltages to the plurality of memory cells, and sensing the plurality of memory cells while the two or more different bit line voltages are applied to the plurality of memory cells. The bit line voltages applied during the program verify operation may allow a first set of the plurality of memory cells to be sensed at a first voltage level while a second set of the plurality of memory cells are sensed at a second voltage level different from the first voltage level.

Abstract: A method is provided for programming a non-volatile memory. The method includes programming memory cells for even bit lines by programming the memory cells into a plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to a plurality of target data states. The method also includes programming memory cells for odd bit lines by programming the memory cells into the plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to the plurality of target data states.

Abstract: A ring with a biometric sensor is provided. In one embodiment, the ring comprises a ring body, a biometric sensor positioned in the ring body and configured to sense a biometric feature, a memory configured to store a biometric feature of an authorized user, and a controller. The controller is configured to determine whether the biometric feature sensed by the biometric sensor matches the biometric feature stored in the memory, and in response to determining that the biometric feature sensed by the biometric sensor matches the biometric feature stored in the memory, enable a function of the ring.

Abstract: A method of forming a shallow trench isolation trench in a semiconductor substrate is described. The method includes forming a trench in a region of the substrate, forming a first dielectric material in the trench, forming a second dielectric material above the first dielectric material, forming a first air gap in the first dielectric material in the trench, and forming a second air gap in the second dielectric material above the first air gap.

Abstract: Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being executed along with flag(s) indicative of the progress executing the command (e.g., command has begun and/or completed execution). When a power failure occurs, the memory device controller may poll the memory integrated circuit chips for the address/flags information to determine whether (or where) the command abort occurred. Thus, relying on the address/flag(s), the memory device controller may more quickly or easily determine whether a command abort has occurred.

Abstract: A non-volatile storage system includes a three dimensional structure comprising vertical columns of memory cells and a managing circuit in communication with the vertical columns The managing circuit applies one or more patterns of stress voltages to the vertical columns, with different voltages applied to each vertical column of pairs of adjacent vertical columns being tested for shorts. The managing circuit tests for a short in the pairs of adjacent vertical columns after applying the one or more patterns of stress voltages. In one embodiment, the test may comprise programming a memory cell in each vertical column with data that matches the pattern of stress voltages, reading from the memory cells and determining whether data read matches data programmed. The applying of the stress voltages and the testing can be performed as part of a test during manufacturing or in the field during user operation.

Abstract: A storage device with a memory may include read disturb detection for open blocks. An open or partially programmed block may develop read disturb errors from reading of the programmed portion of the open block. The detection of any read disturb effects may be necessary for continued programming of the open block and may include verifying that wordlines in the unprogrammed portion of the open block are in the erase state. A modified erase verify operation for the open block is used in which programmed wordlines are subject to a higher erase verify read voltage, while the unprogrammed wordlines are subject to an erase verify bias voltage.

Abstract: A non-volatile memory device is provided that includes a gap in one of the layers of the inter-gate dielectric. One embodiment comprises a plurality of active areas, isolation regions between the active areas, a tunnel oxide layer above the active areas, a floating gate layer above the tunnel oxide layer, a control gate layer above the floating gate layer, and an inter-gate dielectric between the control gate layer and the floating gate layer. The inter-gate dielectric, which in one embodiment includes a SiN layer, is positioned above the isolation regions with gaps in the SiN layer over the isolation regions. Processes for manufacturing are also disclosed.

Abstract: Techniques for forming 3D memory arrays are disclosed. Memory openings are filled with a sacrificial material, such as silicon or nitride. Afterwards, a replacement technique is used to remove nitride from an ONON stack and replace it with a conductive material such as tungsten. Afterwards, memory cell films are formed in the memory openings. The conductive material serves as control gates of the memory cells. The control gate will not suffer from corner rounding. ONON shrinkage is avoided, which will prevent control gate shrinkage. Block oxide between the charge storage region and control gate may be deposited after control gate replacement, so the uniformity is good. Block oxide may be deposited after control gate replacement, so TiN adjacent to control gates can be thicker to prevent fluorine attacking the insulator between adjacent control gates. Therefore, control gate to control gate shorting is prevented.

Abstract: A method of forming a shallow trench isolation trench in a semiconductor substrate is described. The method includes forming a trench in a region of the substrate, forming a liner in the trench, wherein the liner includes a first dielectric material, adhering a halogen element to the liner, forming a second dielectric material in the trench, annealing the first dielectric material and the second dielectric material, exposing a portion of a surface of the second dielectric material, and isotropically etching the exposed portion of the surface of the second dielectric material to form an air gap in the shallow trench isolation trench.

Abstract: A storage device with a memory may include memory block health monitoring and behavior tracking Each memory block may be analyzed based on one or more dummy wordlines within the block may not be accessible for normal data storage. The dummy wordlines may be programmed with a known data pattern that can be tracked and analyzed for potential errors, which may be used as representation of the health of the memory block. Adjustments can be made to the operating parameters (e.g. read voltages) to optimize each memory block based on its error analysis.

Abstract: Systems and methods for detecting a file of a predetermined size or greater are disclosed. Files may be downloaded to a storage device via a data stream. The storage device may analyze one or more aspects of the data stream, such as throughput and consistency, in order to determine whether the file is of a predetermined size or greater. In response to determining that the data stream includes a file of at least a predetermined size, the storage device may take one or more actions. One action is to store part or all of the file in a hybrid block, which is a block in non-volatile memory that is accessed (e.g., programmed and/or erased) in a different way than its designation. For example, a block originally designated for multi-level cell (MLC) storage may be programmed for single-level cell (SLC) storage, which is quicker than for MLC. In this way, the storage device may be able to store the downloaded file, with a certain throughput and consistency, without loss of data.

Abstract: Systems and methods for utilizing wear leveling windows with non-volatile memory systems are disclosed. In one implementation, a memory management module of a non-volatile memory system compares a metric reflecting wear of a memory block to a wear leveling window and determines whether a wear leveling indicator associated with the memory block restricts performing a wear leveling operation on the memory block. The memory management module performs a wear leveling operation on the memory block in response to determining that the metric reflecting wear of the memory block falls outside the wear leveling window and determining that the wear leveling indicator does not restrict performing a wear leveling operation on the memory block. After performing the wear leveling operation, the memory management module places the memory block on a free block list.

Abstract: Circuitry may be used to detect and prevent short circuits in removable or connectable media, such as memory cards. The media may be any device or component with connections to another device, such as a host device that receives a memory card. The host device may connect with the media through connectors (which may include a plurality of pads) that facilitate a connection. If the connection between the host device and the media is improper or misaligned because the respective connectors/pads do not connect properly, then there may be a short circuit. A short circuit detector can both detect and prevent this short circuit.

Abstract: An input/output interface circuit is provided for a memory device. The input/output interface circuit receives a first control signal and a second control signal, and provides an output clock signal. The input/output interface circuit includes a plurality of circuit blocks coupled in series, the a plurality of circuit blocks including an input terminal coupled to the first control signal and the second control signal, and an output terminal providing the output clock signal, a plurality of power switch transistors, each power switch transistor including a control terminal and coupled between a corresponding one of the circuit blocks and a power supply terminal, and a plurality of switch control circuits, each switch control circuit coupled to the control terminal of a corresponding one of the power switch transistors. The switch control circuits are configured to activate the circuit blocks in a first predetermined order and deactivate the circuit blocks in a second predetermined order.

Abstract: Sensing techniques and associated circuitry are provided for use with a memory device. The techniques are suited for sensing operations involving even-numbered or odd-numbered bit lines. In one approach, a mapping between caches and sense amplifiers in a sensing circuit is modified by using dual data buses. One bus is used for same-tier transfers and the other is used for cross-tier transfers. Each tier comprises a set of sense amplifiers and a corresponding set of caches. This approach does not require a modification of the input/output path which is connected to the sensing circuitry.

Abstract: Sensing techniques and associated circuitry are provided for use with a memory device. The techniques are suited for sensing operations involving even-numbered or odd-numbered bit lines. In one approach, the sensing circuitry includes left and right hand portions which have separate cache access lines, but are connected to a common output bus. A full data word can be output at a time by using a half word from the left hand portion and a half word from the right hand portion. Or, the sensing circuitry can be configured so that a full data word is output at a time from the left or right hand portion. One implementation provides an N-bit bus and N input paths for each of the left and right hand portions. Another implementation provides an N-bit bus and N/2 input paths for each of the left and right hand portions.

Abstract: A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer circuit is connected to a data bus and the access circuitry to convert data between a (word-wise) serial format on the bus and (multi-word) parallel format for the access circuitry. Column redundancy circuitry is connect to the serializer/deserializer circuit to provide defective column information about the array. In converting data from a serial to a parallel format, the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. In converting data from a parallel to a serial format the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column.

Abstract: A memory system and method for differential thermal throttling are disclosed. In one embodiment, a memory system is provided comprising a memory and a controller. The controller is configured to receive a command to perform an operation in the memory and analyze the command to determine whether thermal throttling the memory system would result in an unacceptable impact on user experience. In response to determining that thermal throttling the memory system would result in an unacceptable impact on user experience, the controller executes the command. In response to determining that thermal throttling the memory system would not result in an unacceptable impact on user experience, the controller thermal throttles the memory system. Other embodiments are provided.

Abstract: A control circuit, in communication with non-volatile memory cells, is configured to distinguish and classify the memory cells into the different subsets of memory cells based on programming performance. Based on the classifying, the control circuit applies different programming signals to different subsets of the memory cells being programmed to a common data state.