Abstract: Methods and apparatuses for applying different voltages to an I/O interface (such as to the pads of the I/O interface) and determining the data integrity of communicating data (either transmitting to or receiving data from) to another device is disclosed. Data integrity may be measured in one of several ways, such as the window (or timing) at which data can be transmitted correctly using the different voltages. The determined data integrity may be compared with a minimum data integrity, such as a minimum window. In the event that the determined data integrity is greater or better than the minimum data integrity, then the voltage may be reduced and the data integrity determination may be performed again. In this way, the voltage applied to the I/O interface may be reduced while still meeting the minimum data integrity requirements.

Abstract: Programming non-volatile memory includes applying a series of programming pulses to the memory cells as part of a coarse/fine programming process. Between programming pulses, memory cells in the coarse phase are verified for a coarse phase verify level for a target data state and memory cells in the fine phase are verified for a fine phase verify level for the target data state, both in response to a single reference voltage applied on a common word line. For a memory cell in the coarse phase that has been verified to have reached the coarse phase verify level, the memory cell will be temporarily inhibited from programming for a next programming pulse and switched to the fine phase.

Abstract: Fabrication techniques for a three-dimensional stack memory device remove the charge-trapping material from the select gate transistors and the dummy memory cells to avoid unintentional programming which increases the threshold voltage. In one approach, a stack is formed with a sacrificial material for the a) control gate layers of the select gate transistors and the dummy memory cells and the b) control gate layers of the data memory cells. A slit is formed to allow etchants to be introduced to selectively remove the sacrificial material and then the charge-trapping material for the select gate transistors and dummy memory cells. A protective layer is provided partway in the slit, or the slit is etched in two steps.

Abstract: A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer circuit is connected to a data bus and the access circuitry to convert data between a (word-wise) serial format on the bus and (multi-word) parallel format for the access circuitry. Column redundancy circuitry is connect to the serializer/deserializer circuit to provide defective column information about the array. In converting data from a serial to a parallel format, the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. In converting data from a parallel to a serial format the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column.

Abstract: A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The verifying programming of the plurality of memory cells includes verifying programming for a first data state using a verify operation for a second data state. In one embodiment, the one or more control circuits are also configured to sense whether different memory cells of the plurality of memory cells are in different data states by applying different bit line voltages to the different memory cells.

Abstract: A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The one or more control circuits are configured to apply a reference voltage to the memory cells. While applying the reference voltage to the plurality of memory cells, the one or more control circuits are configured to sense whether different memory cells of the plurality of memory cells are in different data states by applying different bit line voltages to different bit lines connected to the different memory cells.

Abstract: A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a substrate having a solder mask. A plurality of pillar bases are formed on the solder mask, and a plurality of solder pillars are applied to the pillar bases. The plurality of solder pillars support one or more semiconductor die above the substrate and the number of solder pillars prevent stresses in the one or more semiconductor die which could otherwise damage the semiconductor die.

Abstract: Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some cases, prior to a first memory die of the plurality of memory die performing a particular memory operation (e.g., a programming operation), the first memory die may poll other memory die of the plurality of memory die to determine a total peak power supply current for the plurality of memory die. In response to detecting that the total peak power supply current for the plurality of memory die is at or above a peak current threshold (e.g., more than 200 mA), the first memory die may delay the performance of the particular memory operation or slow down the performance of the particular memory operation.

Abstract: A memory system may use adaptive trimming to control throughput and traffic from the host to/from the memory. The trimming parameters of memory may be adaptively changed based on the data rate from the host. The programming speed may be slowed in order to reduce wear and improve endurance. In particular, the data rate for the transfer of data from a data buffer to the memory (e.g. NAND flash) may be matched to the host data rate. This programming speed reduction may be triggered upon prediction of idle times in the host bus.

Abstract: Techniques are provided for reducing program disturb in a 3D memory device. The techniques include compensating for a temperature dependence of program disturb. The techniques may include compensating for how program disturb depends on the location of the word line that is selected for programming. In one aspect, the voltage that is applied to the control gates drain side select transistors of unselected NAND strings is adjusted during programming based on temperature. Greater temperature compensation may be applied when the selected word line is closer to the drain side select transistors.

Abstract: Disclosed herein is 3D memory with vertical NAND strings having a III-V compound channel, as well as methods of fabrication. The III-V compound has at least one group III element and at least one group V element. The III-V compound provides for high electron mobility transistor cells. Note that III-V materials may have a much higher electron mobility compared to silicon. Thus, much higher cell current and overall cell performance can be achieved. Also, the memory device may have better read-write efficiency due to much higher carrier mobility and velocity. The tunnel dielectric of the memory cells may have an Al2O3 film in direct contact with the III-V NAND channel. The drain end of the NAND channel may be a metal-III-V alloy in direct contact with a metal region. The body of the source side select transistor could be formed from the III-V compound or from crystalline silicon.

Abstract: In one embodiment, a memory system is provided comprising a memory die and a controller. The memory die comprises a non-volatile memory, a data latch, and an on-chip randomizer. The controller is configured to send a command to the memory die to cause the on-chip randomizer to store random data in the data latch and send data to the memory die to overwrite some, but not all, of the random data in the data latch, wherein the memory die is configured to transfer the data and random data stored in the data latch to the non-volatile memory. Other embodiments are provided.

Abstract: Disclosed herein is 3D memory with vertical NAND strings having a III-V compound channel, as well as methods of fabrication. The III-V compound has at least one group III element and at least one group V element. The III-V compound provides for high electron mobility transistor cells. Note that III-V materials may have a much higher electron mobility compared to silicon. Thus, much higher cell current and overall cell performance can be achieved. Also, the memory device may have better read-write efficiency due to much higher carrier mobility and velocity. The tunnel dielectric of the memory cells may have an Al2O3 film in direct contact with the III-V NAND channel. The drain end of the NAND channel may be a metal-III-V alloy in direct contact with a metal region. The body of the source side select transistor could be formed from the III-V compound or from crystalline silicon.

Abstract: A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench has a first tab extension and a second tab extension. The first tab extension is disposed at a top portion of the shallow trench isolation trench, and extends in a first direction from the shallow trench isolation trench. The second tab extension is disposed at a top portion of the shallow trench isolation trench, and extends in a second direction from the shallow trench isolation trench.

Abstract: Techniques are provided for operating a memory device which detect word line short circuits, such as short circuits between adjacent word lines. In an example implementation, during a programming operation, the number of program loops used to complete programming or reach another programming milestone for WLn are counted. If the number of program loops exceeds a loop count limit, the memory cells of WLn+1 are evaluated to determine whether a short circuit is present. The evaluation involves a read operation which counts erased state memory cells in the upper tail of the Vth distribution of WLn+1. If the count exceeds a bit count limit, it is concluded that a short circuit exits between WLn and WLn+1, and a corrective action is taken. The loop count limit is adjusted lower as the number of program-erase cycles increases.

Abstract: A non-volatile storage system includes a plurality of non-volatile storage elements arranged in two dimensional or three dimensional structures. The system applies programming to the non-volatile storage elements and performs verification of the programming. The verification includes performing a multi-strobe sensing operation to test for multiple data states while applying a common word line voltage.

Abstract: An impedance calibration circuit is provided for off-chip driver/on-die termination circuits. The impedance calibration circuit includes a first circuit that includes first PMOS transistors coupled in parallel between a power supply terminal and a first output terminal, second PMOS transistors coupled in parallel between the power supply terminal and a second output terminal, first NMOS transistors coupled in parallel between the second output terminal and a GROUND terminal, a third PMOS transistor coupled in parallel with the first PMOS transistors between a power supply terminal and a first output terminal, and a second NMOS transistor coupled in parallel with the first NMOS transistors between the second output terminal and a GROUND terminal.

Abstract: Methods for precharging bit lines using closed-loop feedback are described. In one embodiment, a sense amplifier may include a bit line precharge circuit for setting a bit line to a read voltage prior to sensing a memory cell connected to the bit line. The bit line precharge circuit may include a first transistor in a source-follower configuration with a first gate and a first source node electrically coupled to the bit line. By applying local feedback from the first source node to the first gate, the bit line settling time may be reduced. In some cases, a first voltage applied to the first gate may be determined based on a first current drawn from the first bit line. Thus, the first voltage applied to the first gate may vary over time depending on the conductivity of a selected memory cell connected to the bit line.

Abstract: Suspended charge storage regions are utilized for non-volatile storage to decrease parasitic interferences and increase charge retention in memory devices. Charge storage regions are suspended from an overlying intermediate dielectric material. The charge storage regions include an upper surface and a lower surface that extend in the row and column directions. The upper surface of the charge storage region is coupled to the overlying intermediate dielectric material. The lower surface faces the substrate surface and is separated from the substrate surface by a void. The charge storage region includes a first vertical sidewall and a second vertical sidewall that extend in the column direction and a third vertical sidewall and fourth vertical sidewall that extend in the row direction. The first, second, third, and fourth vertical sidewall are separated from neighboring features of the non-volatile memory by the void. The void may include a vacuum, air, gas, or a liquid.

Abstract: Systems and methods are provided for acquiring status information from a plurality of memory die. An apparatus is provided that includes a plurality of memory die and a memory controller. The memory controller is configured to broadcast a first status command to the plurality of memory die, receive a first status response concurrently from the plurality of memory die based on the first status command, and send a repair command to one or more of the plurality of memory die in response to the first status response not satisfying first predetermined status criteria.