Abstract: Various embodiments provide semiconductor structures and their fabrication methods. An SRAM memory cell can include at least one semiconductor structure, and an SRAM memory can include at least one SRAM memory cell. An exemplary semiconductor structure can include at least two adjacent transistors formed on a semiconductor substrate. An opening can be formed and surrounded by gates of the two adjacent transistors and a doped region formed between the gates of the two adjacent transistors. A conductive layer can be formed to at least partially cover a bottom and a sidewall of the opening to electrically connect a gate of one transistor with the doped region of the other transistor of the two adjacent transistors.

Abstract: Various embodiments provide methods and systems for making and/or cleaning semiconductor devices. In one embodiment, a semiconductor device can be formed including a metal layer and a photoresist polymer. During formation, the semiconductor device can be cleaned in a cleaning chamber by a first cleaning solution provided from a solution supply device. After this cleaning process, a second cleaning solution containing metal ions and/or polymer residues can be produced and processed in a solution processing device to at least partially remove the metal ions and/or polymer residues to produce a third cleaning solution for re-use. In an exemplary fabrication or cleaning system, the solution processing device may be configured connecting to either an inlet or an outlet of the cleaning chamber. After cleaning, the semiconductor device can be processed to include a metal plug or an interconnect wiring.

Abstract: A method is provided for fabricating small pitch patterns. The method includes providing a semiconductor substrate, and forming a target material layer having a first region and a second region on the semiconductor substrate. The method also includes forming a plurality of discrete first sacrificial layers on the first region of the target material layer and a plurality of discrete second sacrificial layers on the second region of the target material layer, and forming first sidewall spacers on both sides of the discrete first sacrificial layers and the discrete second sacrificial layers. Further, the method includes removing the first sacrificial layers and the second sacrificial layers, and forming second sidewall spacers. Further, the method also includes forming discrete repeating patterns in the first region of the target material layer and a continuous pattern in the second region of the target material layer.

Abstract: Various embodiments provide semiconductor structures and their fabrication methods. An SRAM memory cell can include at least one semiconductor structure, and an SRAM memory can include at least one SRAM memory cell. An exemplary semiconductor structure can include at least two adjacent transistors formed on a semiconductor substrate. An opening can be formed and surrounded by gates of the two adjacent transistors and a doped region formed between the gates of the two adjacent transistors. A conductive layer can be formed to at least partially cover a bottom and a sidewall of the opening to electrically connect a gate of one transistor with the doped region of the other transistor of the two adjacent transistors.

Abstract: An alignment method includes dividing a wafer into a plurality of regions including a first region and a second region, and each region contains a plurality chip areas. The method also includes obtaining alignment offset values for the first region, and determining a first alignment compensation equation for the first region. The method also includes obtaining alignment offset values for the second region, and determining a second alignment compensation equation for the second region. Further, the method includes determining whether a chip area to be exposed is in the first region or the second region, when the chip area is in the first region, using the first alignment compensation equation to adjust alignment of the wafer and, when the chip area is in the second region, using the second alignment compensation equation to adjust the alignment of the wafer.

Abstract: Various embodiments provide voltage regulator circuitry and devices. An exemplary voltage regulator circuitry can include a current comparing unit configured to convert an output voltage from a charge pump to a current and to compare the current with at least two different reference currents to generate a comparison result. A logic controller can be configured to generate a clock frequency adjustment signal based on the comparison result. A programmable clock unit can be configured to adjust a frequency of a clock signal according to the clock frequency adjustment signal to send the clock signal to the charge pump. Accordingly, the disclosed voltage regulator device can have reduced power consumption and improved reliability.

Abstract: This application discloses a Fin FET structure and a method for forming the same. In the Fin FET structure, there are lower stress spacers disposed over the lower portion of the fin's opposite sidewalls, asserting one stress type to suppress the carrier mobility; there are also upper stress spacers disposed over the upper portion of the fin's opposite sidewalls, asserting an opposite stress type to increase the carrier mobility. Therefore, the leakage current in the fin FET is reduced and the device performance is improved. In the method, the stress spacers are formed by depositing stress layers and etching back the stress layers, where stress types and magnitudes are controllable, resulting in a simple process.

Abstract: Various embodiments provide transistors and fabrication methods. An exemplary transistor can include a silicon nitride layer disposed between a gate dielectric layer and a gate electrode layer. The silicon nitride layer can have a first surface in contact with the gate dielectric layer and a second surface in contact with the gate electrode layer. The second surface can include silicon atoms having a concentration higher than the first surface. A sidewall spacer can be formed on the semiconductor substrate along sidewalls of each of the gate electrode layer, the silicon nitride layer, and the gate dielectric layer. The disclosed transistor can have a reduced turn-on voltage with reduced power consumption.

Abstract: A method is provided for fabricating small pitch patterns. The method includes providing a semiconductor substrate, and forming a target material layer having a first region and a second region on the semiconductor substrate. The method also includes forming a plurality of discrete first sacrificial layers on the first region of the target material layer and a plurality of discrete second sacrificial layers on the second region of the target material layer, and forming first sidewall spacers on both sides of the discrete first sacrificial layers and the discrete second sacrificial layers. Further, the method includes removing the first sacrificial layers and the second sacrificial layers, and forming second sidewall spacers. Further, the method also includes forming discrete repeating patterns in the first region of the target material layer and a continuous pattern in the second region of the target material layer.

Abstract: An exposure method and an exposure device are provided. An exemplary exposure device includes a stage, a first clamp holder, a second clamp holder, an optical projection unit, a first alignment detection unit, and/or a second alignment detection unit. The stage includes a first region and a second region. The first clamp holder is located in the first region and adapted for holding a first substrate, and the second clamp holder is located in the second region and adapted for holding a second substrate. The optical projection unit is located above the stage and adapted for exposure of the first substrate or the second substrate. The first alignment detection unit is adapted for detecting alignment marks of the first substrate. The second alignment detection unit is adapted for detecting alignment marks of the second substrate. The exposure device can accurately position the stage and improve production yield.

Abstract: A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate, forming a first dielectric layer on a surface of the semiconductor substrate based on a first-type oxidation, and forming a high-K dielectric layer on a surface of the first dielectric layer. The method also includes performing a first thermal annealing process to remove the first dielectric layer between the semiconductor substrate and the high-K dielectric layer such that the high-K dielectric layer is on the surface of the semiconductor substrate. Further, the method includes performing a second thermal annealing process to form a second dielectric layer on the surface of the semiconductor substrate between the semiconductor substrate and the high-K dielectric layer, based on a second-type oxidation different from the first-type oxidation, such that high-K dielectric layer is on the second dielectric layer instead of the first dielectric layer.

Abstract: Various embodiments provide an MOS transistor, a formation method thereof, and an SRAM memory cell circuit. An exemplary MOS transistor can include a channel region including an asymmetric stressing layer having a stress gradually varied from a compressive stress to a tensile stress or from a tensile stress to a compressive stress from a first end of the channel region adjacent to a source region to a second end of the channel region adjacent to a drain region. The MOS transistor can be used as a transfer transistor in an SRAM memory cell circuit to increase a source-drain saturation current in a write operation and to reduce a source-drain saturation current in a read operation. Read and write margins of the SRAM can be increased.

Abstract: Various embodiments provide semiconductor devices including high-K dielectric layer(s) and fabrication methods. An exemplary high-K dielectric layer can be formed by providing a semiconductor substrate including a first region and a second region, and forming a first silicon oxide layer on the semiconductor substrate in the first region. The semiconductor substrate can then be placed in an atomic layer deposition (ALD) chamber to repeatedly perform a selective ALD process. The selective ALD process can include an etching process and/or a purging process in the ALD chamber. By repeatedly performing the selective ALD process, a first high-K dielectric layer can be selectively formed on the first silicon oxide layer in the first region, exposing the semiconductor substrate in the second region.

Abstract: Various embodiments provide transistors and their fabrication methods. An exemplary method for forming a transistor includes removing a dummy gate to form a trench over a semiconductor substrate. A high-k dielectric layer can be conformally formed on surface of the trench and then be fluorinated to form a fluorinated high-k dielectric layer. A functional layer can be formed on the fluorinated high-k dielectric layer and a metal layer can be formed on the functional layer to fill the trench with the metal layer. Due to fluorination of the high-k dielectric layer, negative bias temperature instability of the formed transistor can be reduced and oxygen vacancies can be passivated to reduce positive bias temperature instability of the transistor.

Abstract: The present disclosure provides a lithography machine and a scanning and exposing method thereof. According to the scanning and exposing method, the scanning and exposing process for a whole wafer includes two alternately circulated motions: a scanning and exposing motion and a stepping motion; and the scanning and exposing motion is a sinusoidal motion rather than a rapid-acceleration uniform-speed rapid-deceleration scanning and exposing motion in the conventional techniques. During the scanning of a single exposure shot, it may begin to scan the exposure shot once a wafer stage and a reticle stage begin to accelerate from zero speed. And the scanning and exposing may not end until the speeds of the wafer stage and the reticle decrease to zero. Therefore, the effective time of the scanning and exposing in the scanning and exposing motion is greatly increased and the production efficiency of the wafer is improved.

Abstract: A fin field effect transistor (FET) including a fin structure and a method for forming the fin FET are provided. In an exemplary method, the fin FET can be formed by forming at least one fin seed, including a top surface and sidewalls, on a substrate. A first semiconductor layer can then be formed at least on the sidewalls of the at least one fin seed. A second semiconductor layer can be formed on the first semiconductor layer. The second semiconductor layer and the at least one fin seed can be made of a same material. The first semiconductor layer can be removed to form a fin structure including the at least one fin seed and the second semiconductor layer.

Abstract: A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate, and forming a plurality of fins with hard mask layers and an isolation structure. The process also includes forming a first dummy gate layer on the fins and the isolation structure, and polishing the first dummy gate layer until the hard mask layer is exposed. Further, the method includes removing the hard mask layer to expose a top surface of the fins, and forming a second dummy gate material layer on the first dummy gate material layer. Further, the method also includes etching the second dummy gate layer and the first dummy gate layer to form a dummy gate on each of the fins.

Abstract: A fabrication process of a semiconductor device is disclosed. The method includes providing a semiconductor substrate with a first insulation layer formed on the semiconductor substrate and a fin formed on the surface of the first insulation layer, and forming a fully-depleted semiconductor layer on sidewalls of the fin, and the fully-depleted semiconductor layer having a material different from that of the fin. The method also includes forming a second insulation layer covering the fully-depleted semiconductor layer, and removing the fin to form an opening exposing sidewalls of the fully-depleted semiconductor layer. Further, the method includes forming a gate dielectric layer on part of the sidewalls of the fully-depleted semiconductor layer such that the part of the sidewalls of the fully-depleted semiconductor layer form channel regions of the semiconductor device, and forming a gate electrode layer covering the gate dielectric layer.

Abstract: Various embodiments provide transistors and fabrication methods. An exemplary transistor can include a silicon nitride layer disposed between a gate dielectric layer and a gate electrode layer. The silicon nitride layer can have a first surface in contact with the gate dielectric layer and a second surface in contact with the gate electrode layer. The second surface can include silicon atoms having a concentration higher than the first surface. A sidewall spacer can be formed on the semiconductor substrate along sidewalls of each of the gate electrode layer, the silicon nitride layer, and the gate dielectric layer. The disclosed transistor can have a reduced turn-on voltage with reduced power consumption.

Abstract: Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.