Patents Assigned to Semiconductor Manufacturing International Corp
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Patent number: 9105632Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a plurality of first doped regions and second doped regions; and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a first gate dielectric layer and a second gate dielectric layer; and forming a first metal gate and a second metal gate on the first gate dielectric layer and the second gate dielectric layer, respectively. Further, the method includes forming a third dielectric layer on the second metal gate; and forming a second dielectric layer on the first dielectric layer. Further, the method also includes forming at least one opening exposing at least one first metal gate and one first doped region; and forming a contact layer contacting with the first metal gate and the first doped region to be used as a share contact structure.Type: GrantFiled: October 21, 2014Date of Patent: August 11, 2015Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPInventor: Zhongshan Hong
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Patent number: 9099558Abstract: This application discloses a Fin FET structure and a method for forming the same. In the Fin FET structure, there are lower stress spacers disposed over the lower portion of the fin's opposite sidewalls, asserting one stress type to suppress the carrier mobility; there are also upper stress spacers disposed over the upper portion of the fin's opposite sidewalls, asserting an opposite stress type to increase the carrier mobility. Therefore, the leakage current in the fin FET is reduced and the device performance is improved. In the method, the stress spacers are formed by depositing stress layers and etching back the stress layers, where stress types and magnitudes are controllable, resulting in a simple process.Type: GrantFiled: October 16, 2012Date of Patent: August 4, 2015Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.Inventor: Wayne Bao
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Patent number: 9087836Abstract: A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having an oxide layer on a surface of the semiconductor substrate, and removing the oxide layer to expose the surface of the semiconductor substrate. The method also includes performing a thermal annealing process on the semiconductor substrate using an inert gas as a thermal annealing protective gas after removing the oxide layer, and forming an insulating layer on the semiconductor substrate after performing the thermal annealing process. Further, the method includes forming a high-K gate dielectric layer on a surface of the insulating layer, and forming a protective layer on a surface of the high-K gate dielectric layer.Type: GrantFiled: October 15, 2014Date of Patent: July 21, 2015Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.Inventor: Hualong Song
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Patent number: 9070557Abstract: A semiconductor structure including a double patterned structure and a method for forming the semiconductor structure are provided. A negative photoresist layer is formed on a positive photoresist layer, which is formed over a substrate. An exposure process is performed to form a first exposure region in the positive photoresist layer and to form a second exposure region in the negative photoresist layer in response to a first and a second intensity thresholds of the exposure energy. A negative-tone development process is performed to remove portions of the negative photoresist layer to form first opening(s). The positive photoresist layer is then etched along the first opening(s) to form second opening(s) therein. A positive-tone development process is performed to remove the first exposure region therefrom to form a double patterned positive photoresist layer.Type: GrantFiled: March 7, 2013Date of Patent: June 30, 2015Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.Inventors: Daniel Hu, Ken Wu, Yiming Gu
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Patent number: 9054021Abstract: A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate, and forming a metal layer on the semiconductor substrate. The method also includes forming a silicon layer having at least one layer of graphene-like silicon on the metal layer, and forming a metal oxide layer by oxidizing a portion of the metal layer underneath the silicon layer. Further, the method includes forming a source region and a drain region connecting with the silicon layer.Type: GrantFiled: March 15, 2013Date of Patent: June 9, 2015Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPInventors: Deyuan Xiao, Emily Shu
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Patent number: 9029224Abstract: A method is provided for fabricating a High-K layer. The method includes providing a substrate, applying a first precursor gas on the substrate such that the substrate absorbs first precursor gas molecules in a chemical absorption process, and removing the unabsorbed first precursor gas using a first inert gas. The method also includes applying a second precursor gas on the substrate, and forming a first thin film on the substrate as a reaction product of the second precursor gas and the absorbed first precursor gas molecules. Further, the method includes removing unreacted second precursor gas and byproducts using a second inert gas, and forming a high-K layer on the substrate by forming a plurality of the first thin films layer-by-layer.Type: GrantFiled: January 8, 2013Date of Patent: May 12, 2015Assignee: Semiconductor Manufacturing International Corp.Inventors: Yong Chen, Yonggen He
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Patent number: 9018731Abstract: Various embodiments provide inductor devices and fabrication methods. An exemplary inductor device can include a plurality of planar spiral wirings isolated by a dielectric layer. The planar spiral wirings can be connected by conductive pads formed over the dielectric layer and by conductive plugs formed in the dielectric layer. In one embodiment, a third planar spiral wiring can be formed over a second planar spiral wirings that is formed over a first planar spiral wiring. The third planar spiral wiring can be configured in parallel with the first third planar spiral wiring. The second planar spiral wiring can be configured in series with the first and third planar spiral wirings configured in parallel.Type: GrantFiled: October 13, 2014Date of Patent: April 28, 2015Assignee: Semiconductor Manufacturing International CorpInventors: Jenhao Cheng, Xining Wang, Ling Liu
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Patent number: 8980718Abstract: A method is provided for fabricating a PMOS transistor. The method includes providing a semiconductor substrate, and forming a dummy gate structure at least having a dummy gate, a high-K dielectric layer, and a sidewall spacer surrounding the high-K dielectric layer and the dummy gate on the semiconductor substrate. The method also includes forming a source region and a drain region in the semiconductor substrate at both sides of the dummy gate structure by an ion implantation process, and performing a first annealing process to enhance the ion diffusion. Further, the method includes forming an interlayer dielectric layer leveling with the surface of the dummy gate, and forming a trench by removing the dummy gate. Further, the method also includes performing a second annealing process, and forming a metal gate in the trench.Type: GrantFiled: January 10, 2013Date of Patent: March 17, 2015Assignee: Semiconductor Manufacturing International Corp.Inventor: Yong Chen
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Patent number: 8980729Abstract: An SOI substrate and a method for forming the SOI substrate are provided. An SOI substrate can be formed by forming a silicon-germanium layer on a first baseplate. A top silicon layer can be formed on the silicon-germanium layer. A first insulating layer can be formed on the top silicon layer. An ion implanted layer can be formed in one of the silicon-germanium layer and the first baseplate. A second baseplate can be bonded to the first insulating layer. A first annealing process can be performed to anneal and split the one of the silicon-germanium layer and the first baseplate at the ion implanted layer. The silicon-germanium layer can be removed from the top silicon layer to expose the top silicon layer and to form the SOI substrate comprising the first insulating layer formed between the top silicon layer and the second baseplate.Type: GrantFiled: March 12, 2013Date of Patent: March 17, 2015Assignee: Semiconductor Manufacturing International Corp.Inventor: Aries Chen
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Patent number: 8975642Abstract: Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.Type: GrantFiled: November 27, 2012Date of Patent: March 10, 2015Assignee: Semiconductor Manufacturing International CorpInventors: Neil Zhao, Mieno Fumitake
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Patent number: 8975703Abstract: Various embodiments provide an MOS transistor, a formation method thereof, and an SRAM memory cell circuit. An exemplary MOS transistor can include a semiconductor substrate including a first groove on one side of a gate structure and a second groove on the other side of the gate structure. The first groove can have a sidewall perpendicular to a surface of the semiconductor substrate. The second groove can have a sidewall protruding toward a channel region under the gate structure. A stressing material can be disposed in the first groove to form a drain region and in the second groove to form a source region. Stress generated in the channel region of the MOS transistor can be asymmetric. The MOS transistor can be used as a transfer transistor in an SRAM memory cell circuit to increase both read and write margins of the SRAM memory.Type: GrantFiled: January 11, 2013Date of Patent: March 10, 2015Assignee: Semiconductor Manufacturing International Corp.Inventors: Zhenghao Gan, Junhong Feng
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Patent number: 8975167Abstract: A fabrication process of a semiconductor device is disclosed. The method includes providing a semiconductor substrate with a first insulation layer formed on the semiconductor substrate and a fin formed on the surface of the first insulation layer, and forming a fully-depleted semiconductor layer on sidewalls of the fin, and the fully-depleted semiconductor layer having a material different from that of the fin. The method also includes forming a second insulation layer covering the fully-depleted semiconductor layer, and removing the fin to form an opening exposing sidewalls of the fully-depleted semiconductor layer. Further, the method includes forming a gate dielectric layer on part of the sidewalls of the fully-depleted semiconductor layer such that the part of the sidewalls of the fully-depleted semiconductor layer form channel regions of the semiconductor device, and forming a gate electrode layer covering the gate dielectric layer.Type: GrantFiled: November 27, 2012Date of Patent: March 10, 2015Assignee: Semiconductor Manufacturing International CorpInventor: Zhongshan Hong
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Patent number: 8929051Abstract: An apparatus and a method for holding a wafer are provided in this disclosure. The wafer holding apparatus includes: an electrostatic chuck which has a plurality of zones arranged in a matrix; a plurality of power supply units, each of which is adapted to apply a voltage to the plurality of zones of the electrostatic chuck independently; and a control unit which is adapted to control each of the power supply units independently to start or stop applying the voltage to a corresponding zone of the electrostatic chuck. Surface flatness is improved when the wafer is chucked on the wafer holding apparatus according to the disclosure, and the risk of particles contamination can be reduced when the wafer is flattened and gets back into warpage from flatness.Type: GrantFiled: October 11, 2012Date of Patent: January 6, 2015Assignee: Semiconductor Manufacturing International Corp.Inventor: Emily Shu
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Patent number: 8917489Abstract: An apparatus and a method for holding a wafer are provided in this disclosure. The wafer holding apparatus includes: an electrostatic chuck, the electrostatic chuck having a plurality of concentric zones; a plurality of power supply units, each adapted for applying a voltage to one of the zones of the electrostatic chuck independently; and a control unit, adapted for controlling each of the power supply units independently to start or stop applying the voltage to a corresponding zone of the electrostatic chuck. Surface flatness is improved when the wafer is chucked on the wafer holding apparatus according to the disclosure, and the risk of particle contamination can be reduced when the wafer is flattened and gets back into warpage from flatness.Type: GrantFiled: October 11, 2012Date of Patent: December 23, 2014Assignee: Semiconductor Manufacturing International Corp.Inventor: Emily Shu
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Patent number: 8912545Abstract: A method is provided for fabricating a nanowire-based semiconductor structure. The method includes forming a first nanowire with a first polygon-shaped cross-section having a first number of sides. The method also includes forming a semiconductor layer on surface of the first nanowire to form a second nanowire with a second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number. Further, the method includes annealing the second nanowire to remove a substantial number of vertexes of the second polygon-shaped cross-section to form the nanowire with a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section.Type: GrantFiled: March 15, 2013Date of Patent: December 16, 2014Assignee: Semiconductor Manufacturing International Corp.Inventors: Deyuan Xiao, James Hong
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Patent number: 8901675Abstract: A method is provided for fabricating a CMOS device. The method includes providing a semiconductor substrate having a first active region and a second active region. The method also includes forming a first trench on the first active region using a first barrier layer and a second substitute gate electrode layer to protect a gate region on the second active region, followed by forming a first work function layer and a first metal gate in the first trench. Further, the method includes forming a second trench on the second active region using a second barrier layer to protect the first metal gate structure, followed by forming a second work function layer and a second metal gate in the second trench.Type: GrantFiled: December 14, 2012Date of Patent: December 2, 2014Assignee: Semiconductor Manufacturing International Corp.Inventors: Weihai Bu, Wenbo Wang, Shaofeng Yu, Hanming Wu
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Patent number: 8895389Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a plurality of first doped regions and second doped regions; and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a first gate dielectric layer and a second gate dielectric layer; and forming a first metal gate and a second metal gate on the first gate dielectric layer and the second gate dielectric layer, respectively. Further, the method includes forming a third dielectric layer on the second metal gate; and forming a second dielectric layer on the first dielectric layer. Further, the method also includes forming at least one opening exposing at least one first metal gate and one first doped region; and forming a contact layer contacting with the first metal gate and the first doped region to be used as a share contact structure.Type: GrantFiled: June 17, 2013Date of Patent: November 25, 2014Assignee: Semiconductor Manufacturing International CorpInventor: Zhongshan Hong
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Patent number: 8889516Abstract: A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having an oxide layer on a surface of the semiconductor substrate, and removing the oxide layer to expose the surface of the semiconductor substrate. The method also includes performing a thermal annealing process on the semiconductor substrate using an inert gas as a thermal annealing protective gas after removing the oxide layer, and forming an insulating layer on the semiconductor substrate after performing the thermal annealing process. Further, the method includes forming a high-K gate dielectric layer on a surface of the insulating layer, and forming a protective layer on a surface of the high-K gate dielectric layer.Type: GrantFiled: November 8, 2012Date of Patent: November 18, 2014Assignee: Semiconductor Manufacturing International Corp.Inventor: Hualong Song
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Patent number: 8884399Abstract: Various embodiments provide inductor devices and fabrication methods. An exemplary inductor device can include a plurality of planar spiral wirings isolated by a dielectric layer. The planar spiral wirings can be connected by conductive pads formed over the dielectric layer and by conductive plugs formed in the dielectric layer. In one embodiment, a third planar spiral wiring can be formed over a second planar spiral wirings that is formed over a first planar spiral wiring. The third planar spiral wiring can be configured in parallel with the first third planar spiral wiring. The second planar spiral wiring can be configured in series with the first and third planar spiral wirings configured in parallel.Type: GrantFiled: November 30, 2012Date of Patent: November 11, 2014Assignee: Semiconductor Manufacturing International Corp.Inventors: Jenhao Cheng, Xining Wang, Ling Liu
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Patent number: 8884374Abstract: Various embodiments provide complementary metal-oxide-semiconductor (CMOS) devices and their fabrication methods. A semiconductor substrate is provided to include a first region to form a PMOS transistor and a second region to form an NMOS transistor. One of the first and second regions can include a metal gate structure having a metal top layer. The other of the first and second regions can include an interfacial oxide layer formed on a high-k dielectric layer. A surface of the metal top layer can be oxidized to form a metal oxide top layer covering the metal top layer. The metal oxide top layer and the interfacial oxide layer can be removed by wet etching. A metal gate can be formed on the high-k dielectric layer.Type: GrantFiled: January 18, 2013Date of Patent: November 11, 2014Assignee: Semiconductor Manufacturing International Corp.Inventors: Leo Liu, Allan He