Abstract: A multi-phase clock generator is provided in the application. The multi-phase clock generator includes a first oscillator circuit and a second oscillator circuit. The first oscillator circuit includes a plurality of first delay circuits. The first oscillator circuit receives the first number of multi-phase input clock signals and outputs the second number of first output clock signals, wherein the second number is larger than the first number. The second oscillator circuit is coupled to the first oscillator circuit. The second oscillator circuit includes a plurality of second delay circuits. The second oscillator circuit receives the second number of first output clock signals and outputs the second number of second output clock signals. The number of second delay circuits is less than the number of first delay circuits.

Abstract: A method of an electronic device for controlling power consumption includes the following steps. A busy-waiting command is received, wherein the busy-waiting command indicates that the operating system of a processing device is in a busy-waiting state. The microcode of the busy-waiting command is obtained according to the busy-waiting command. A waiting enabling command is generated and a counting value corresponding to the waiting enabling command is obtained according to the microcode. According to the waiting enabling command, the subsequent microcode is stopped sending to the processing device, so that the processing device enters an idle state, and the counter is enabled to start counting according to the counting value.

Abstract: A performance analysis system includes a picker module and a calculation circuit. The picker module is placed in the processing device to capture a plurality of pieces of time information of a unit circuit of each of a plurality of tasks in the processing device during total execution time of processing the plurality of tasks. The calculation circuit performs an interval analysis operation on the time information. The interval analysis operation includes: calculating an overlap period between a current task and a previous task; and counting time occupied by the unit circuit during the total execution time of processing the tasks by the processing device according to a relation between the current time interval of the current task corresponding to the unit circuit and the overlap period.

Abstract: An operation method of a sleep mode of an electronic device includes the following steps. A first sub-module of a first module sends a sleep command to a second sub-module of the first module and a third sub-module and a fourth sub-module of a second module, wherein the first sub-module includes first and second modes, the second sub-module includes third and fourth nodes, the third sub-module includes fifth and sixth nodes, and the fourth sub-module includes seventh and eighth nodes. The second sub-module, the third sub-module and fourth sub-module execute a sleep sequence in sequence to enter a sleep mode according to the sleep command. The first node sends the sleep command to the second node to execute the sleep sequence to enter the sleep mode. The first node sends the sleep command to the first node to execute the sleep sequence to enter the sleep mode.

Abstract: A method for converting instructions is provided. The method is used in a processor and includes: receiving an instruction, wherein the instruction is an unknown instruction; determining whether the received instruction is a new instruction; and converting the received instruction into at least one old instruction when the received instruction is a new instruction.

Abstract: A bridging module, a data transmission system, and a data transmission method are provided. The bridging module obtains a first read request, and allocates a first location storage space for first return data corresponding to the first read request. The bridging module combines a first master transaction identifier and an address of the first location storage space as a first slave transaction identifier of the first read request, and sends the first read request to a slave device. The bridging module obtains a second read request, and allocates a second location storage space for second return data corresponding to the second read request. The bridging module combines a second master transaction identifier and an address of the second location storage space as a second slave transaction identifier of the second read request, and sends the second read request to the slave device.

Abstract: A bridging module, a data transmission system, and a data transmission method are provided. The bridging module obtains a first read request, and allocates a first data storage space for first return data corresponding to the first read request. The bridging module combines a first master transaction identifier and an address of the first data storage space as a first slave transaction identifier of the first read request, and sends the first read request to a slave device. The bridging module obtains a second read request, and allocates a second data storage space for second return data corresponding to the second read request. The bridging module combines a second master transaction identifier and an address of the second data storage space as a second slave transaction identifier of the second read request, and sends the second read request to the slave device.

Abstract: A method for executing new instructions includes receiving an instruction, and determining whether the received instruction is a new instruction according to an operation code of the received instruction. When the received instruction is a new instruction, the basic decoding information of the received instruction is stored in a private register. And, the system for executing the new instructions enters a system management mode, and simulates the execution of the received instruction according to the basic decoding information stored in the private register in the system management mode; wherein the basic decoding information includes the operation code.

Abstract: A core partition circuit comprises a first decompression circuit, a second decompression circuit, a first switching circuit, an wrapper scanning circuit, a first compression circuit, a second compression circuit and a second switching circuit. The first and second decompression circuits decompress an input signal. The first switching circuit outputs the output signal of the first decompression circuit or the second decompression circuit according to a first control signal. The wrapper scanning circuit receives the output signal of the first decompression circuit or the second decompression circuit to scan the internal or the port of the core partition circuit. The first and second compression circuits respectively compress the internal logic and the port logic of the core partition circuit. The second switching circuit outputs the compressed internal logic or port logic of the core partition circuit according to the first control signal.

Abstract: An electronic device comprises a first processor, a second processor and a communication interface. The first processor operates according to a first clock, and comprises a first time-stamp counter to count the first clock to obtain a first count value. The second processor operates according to a second clock, and comprises a second time-stamp counter to count the second clock to obtain a second count value. The communication interface is coupled between the first processor and the second processor. The first processor periodically sends the first count value to the second processor through the communication interface. When the second processor receives the first count value, the second processor adds a preset deviation value to the first count value to obtain a synchronization value, resets the second count value, and the sum of the synchronization value and the second count value is read by the second processor.

Abstract: A method for executing new instructions includes the following steps. An instruction is received. A determination is made as to whether the received instruction is a new instruction. When the received instruction is the new instruction, a emulation flag is generated. The emulation flag is a first value. A system management interrupt is generated according to the emulation flag. In response to the system management interrupt, entering the system management mode and simulating the execution of the received instruction in the system management mode to generate a simulation execution result. The simulation execution result is stored in a system management memory.

Abstract: A micro-processor circuit and a method of performing neural network operation are provided. The micro-processor circuit is suitable for performing neural network operation. The micro-processor circuit includes a parameter generation module, a compute module and a truncation logic. The parameter generation module receives in parallel a plurality of input parameters and a plurality of weight parameters of the neural network operation. The parameter generation module generates in parallel a plurality of sub-output parameters according to the input parameters and the weight parameters. The compute module receives in parallel the sub-output parameters. The compute module sums the sub-output parameters to generate a summed parameter. The truncation logic receives the summed parameter. The truncation logic performs a truncation operation based on the summed parameter to generate a plurality of output parameters of the neural network operation.

Abstract: Packet routing within a multi-chip processing system is shown. A first chip has a first interconnect bus, and a first microprocessor coupled to the first interconnect bus. The first interconnect bus has a first routing register. When the first microprocessor operates the first chip as a source node to output a packet to be transferred to a destination node, routing information indicating a routing path from the source node to the destination node is written into the first routing register and then loaded from the first routing register to a header of the packet. While being transferred within the multi-chip processing system from the source node to the destination node, the packet is guided along the routing path indicated in the routing information carried in the header of the packet.

Abstract: A method for executing new instructions includes receiving an instruction, and determining whether the received instruction is a new instruction according to an operation code of the received instruction. When the received instruction is a new instruction, the basic decoding information of the received instruction is stored in a private register. And, the system for executing the new instructions enters a system management mode, and simulates the execution of the received instruction according to the basic decoding information stored in the private register in the system management mode; wherein the basic decoding information includes the operation code.

Abstract: A micro-processor circuit and a method of performing neural network operation are provided. The micro-processor circuit is suitable for performing neural network operation. The micro-processor circuit includes a parameter generation module, a compute module and a compare logic. The parameter generation module receives in parallel a plurality of input parameters and a plurality of weight parameters of the neural network operation. The parameter generation module generates in parallel a plurality of sub-output parameters according to the input parameters and the weight parameters. The compute module receives in parallel the sub-output parameters. The compute module sums the sub-output parameters to generate a summed parameter. The compare logic receives the summed parameter. The compare logic performs a comparison operation based on the summed parameter to generate a plurality of output parameters of the neural network operation.

Abstract: An output stage circuit comprising a bias voltage generator, a first amplifier circuit and a second amplifier circuit is provided. The bias voltage generator is coupled to an output terminal of the output stage circuit to generate a bias voltage according to an output voltage of the output terminal. The first amplifier circuit is coupled to the output terminal, a first power supply terminal and the bias voltage generator, receives a first pre-driving signal, a first predetermined voltage and the bias voltage, and determines whether to transmit a first voltage to serve as the output voltage. The second amplifier circuit is coupled to the output terminal, a second power supply terminal and the bias voltage generator, receives a second pre-driving signal, a second predetermined voltage and the bias voltage, and determines whether to transmit a second voltage to serve as the output voltage.

Abstract: A simulation method and a simulation system are provided. The simulation system may be divided into an execution model and a processor model based on a JIT emulation engine. The execution model can call the JIT emulation engine to execute instructions, and obtain influence of instructions on a processor architectural status. The processor model may simulate an internal process of a target processor and determine whether to start/end a speculation. The execution model and the processor model may interact through a specific protocol. After the speculation is started, the simulation method may store an application running scene when the speculation is started, and redirect influence of speculation instructions on a memory to a memory snapshot. After the speculation is ended, the simulation method may also restore the application running scene to a status before the speculation is started, and cancel influence of the speculation instructions on the memory.

Abstract: A voltage regulator includes a first control circuit and a first voltage adjusting circuit. The first control circuit receives an output voltage and generates a first control signal according to the output signal. The first voltage adjusting circuit is coupled to the first control circuit, receives the first control signal, and adjusts the output voltage according to the first control signal.

Abstract: An instruction execution method suitable for being executed by a processor is provided. The first processor comprises a register alias table (RAT) and a reservation station. The instruction execution method includes: a register alias table receives a first micro-instruction and a second micro-instruction and issues the first micro-instruction and the second micro-instruction to the reservation station; and the reservation station assigns one of a plurality of execution units to execute the first micro-instruction, according to the first specific message of the first micro-instruction; and the reservation station assigns one of the execution units to execute the second micro-instruction, according to the second specific message of the second micro-instruction.

Abstract: A prefetcher, an operating method of the prefetcher, and a processor including the prefetcher are provided. The prefetcher includes a prefetch address generating circuit, an address tracking circuit, and an offset control circuit. The prefetch address generating circuit generates a prefetch address based on first prefetch information and an offset amount. The address tracking circuit stores the prefetch address and a plurality of historical prefetch addresses. When receiving an access address, the offset control circuit updates the offset amount based on second prefetch information, the access address, the prefetch address, and the historical prefetch addresses, and provides the prefetch address generating circuit with the updated offset amount.