Abstract: A computing device, a power consumption prediction method thereof, and a non-transitory computer-readable storage medium are provided. In one embodiment, leakage power consumption of a graphics processor is obtained. Switching power consumption data corresponding to the graphics processor running a frame of image is obtained. Switching power consumption is estimated according to the switching power consumption data. Overall power consumption of the graphics processor is obtained according to the leakage power and the switching power consumption. Overall power consumption of the graphics processor processing one frame of image is estimated based on the overall power consumption. Power consumption performance of the graphics processor is therefore predicted in real-time.

Abstract: An instruction execution method includes the following steps: translating a macro-instruction into a first micro-instruction and a second micro-instruction, and marking first binding information on the first micro-instruction, and marking second binding information on the second micro-instruction; and simultaneously retiring the first micro-instruction and the second micro-instruction according to the first binding information and the second binding information. The first micro-instruction and the second micro-instruction are adjacent to one another in the micro-instruction storage space.

Abstract: A data link layer device and a packet encapsulation method are provided. The data link layer device includes a first and a second first-in-first-out (FIFO) module. The first FIFO module receives and stores multiple first data from an upper-layer module, and removes data gaps from the first data to store the first data in a continuous form. When the first FIFO module is not empty, the first FIFO module generates data of different lengths based on the current amount of data stored temporarily in the first FIFO module and a preset data length. When the data queue of the second FIFO module has enough space to receive the first data, the first FIFO module transfers the first data to the second FIFO module, and the first FIFO module transfers a header including the data length to a header queue of the second FIFO module.

Abstract: A processing system includes a cache, a host memory, a CPU and a hardware accelerator. The CPU accesses the cache and the host memory and generates at least one instruction. The hardware accelerator operates in a non-temporal access mode or a temporal access mode according to the access behavior of the instruction. The hardware accelerator accesses the host memory through an accelerator interface when the hardware accelerator operates in the non-temporal access mode, and accesses the cache through the accelerator interface when the hardware accelerator operates in the temporal access mode.

Abstract: A processing system includes at least one core, a plurality of accelerator function unit (AFU) and a memory access unit. The memory access unit includes at least one pipeline resource and an arbitrator. The core develops a plurality of tasks. Each of the AFU is used to execute at least one of the tasks which corresponds to several memory access requests. The arbitrator selects one of the AFUs using a round-robin method at each clock period to transmit a corresponding memory access request of the selected AFU to the pipeline resource, so that the selected AFU executes the memory access request through the pipeline resource to read or write data related to the task.

Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a pair of first contacts and eight second contacts. The pair of first contacts is a pair of differential signal contacts. The second contacts are arranged around the pair of first contacts. Two of the second contacts are arranged along a straight line perpendicular to a connecting line of the pair of first contacts. The position distribution and electrical properties of the other six of the second contacts are symmetrical to each other relative to the straight line.

Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a first contact and six second contacts. The second contacts are arranged around the first contact. When the first contact is a power contact or a ground contact, the second contacts are signal contacts. When the first contact is a signal contact, three of the second contacts are power contacts or ground contacts and are not adjacent to each other.

Abstract: A microprocessor is shown, in which a branch predictor and an instruction cache are decoupled by a fetch-target queue (FTQ). The FTQ stores at least an instruction address whose branch prediction has been finished by the branch predictor. The instruction addresses queued in the FTQ is to be read out later as an instruction-fetching address for the instruction cache. The instruction address that is input into the branch predictor and used for branch prediction leads the instruction-fetching address.

Abstract: A method for operating an apparatus that includes a program memory, a data memory and a status register that holds a status, wherein the status has fields including: a program memory address at which a most recent instruction is fetched from the program memory, a data memory access address at which data has most recently been accessed in the data memory by the apparatus and a repeat count indicating a number of times an operation specified in a current program instruction remains to be performed, the apparatus further including a condition register having condition fields corresponding to the status fields held in the status register, the method including: writing the condition register with a condition including the condition fields; and generating an interrupt request to a processing core in response to detecting that the status held in the status register satisfies the condition specified in the condition register.

Abstract: A programmable apparatus includes a program memory that holds instructions of a program fetched and executed by the apparatus, a data memory that holds data processed by the instructions, a status register that holds a status having fields: a program memory address at which a most recent instruction is fetched from the program memory, a data memory access address at which data has most recently been accessed in the data memory by the apparatus and a repeat count that indicates a number of times an operation specified in a current program instruction remains to be performed. A condition register has condition fields corresponding to the status register fields. Control logic generates an interrupt request to a processing core in response to detecting that the status held in the status register satisfies the condition specified in the condition register.

Abstract: A processing system includes at least one core, several accelerator function units (AFU) and a microcontroller. The core is utilized to operate several processes and develop at least one task queue corresponding to each of the processes. The processing core generates several command packets and pushes them into the corresponding task queue. The AFU executes the command packets. The microcontroller is arranged between the AFU and the core to dispatch the command packet to a corresponding AFU for execution. When the corresponding AFU executes the command packet of a specific process of the processes, the microcontroller assigns the corresponding AFU to execute other command packets in the task queue of the specific process at a higher priority.

Abstract: A time-to-digital convertor comprises a phase frequency detector, a first conversion module, a gated ring oscillator and a counting module. The phase frequency detector outputs a first detection signal and a second detection signal according to a first clock signal and a second clock signal. The first conversion module receives the first detection signal and the second detection signal to generate a first control signal and a second control signal. The gated ring oscillator receives the first and second control signals and outputs a plurality of clock signals according to the pulse width difference between the first and second control signals. The counting module counts the plurality of clock signals to generate the phase difference between the first and second clock signals.

Abstract: A multi-die and multi-core computing platform in which multiple dies share the same storage device for firmware code storage is shown. After a slave die loads #1 firmware code from the storage device through a bus, the right to use the bus is released by the slave die and the slave die outputs a #0 enable signal to a master die. According to the #0 enable signal, the master die gains the right to use the bus. Through the bus, the master die loads #0 firmware code from the storage device. The slave die executes the #1 firmware code and the master die executes the #0 firmware code to initialize a link between the master and slave dies.

Abstract: An apparatus includes a first memory, processing units that access the first memory, and a counter that, for each period of a sequence of periods, holds an indication of accesses to the first memory during the period; and control logic that, for each period of the sequence of periods, monitors the indication to determine whether it exceeds the threshold and, if so, stalls the processing units from accessing the first memory for a remaining portion of the period.

Abstract: A booting technology for a multi-die and multi-core computing platform is shown. A storage device stores number 1 firmware code and number 0 firmware code. A master die is coupled to the storage device through a bus and accesses the number 1 firmware code from the storage device through the bus. A first slave die is also coupled to the storage device through the bus. However, instead of accessing the storage device for the number 1 firmware code, the first slave die monitors the bus and retrieves the number 1 firmware code, accessed by the master die, from the bus. The master die further accesses the number 0 firmware code from the storage device through the bus. The master die executes the number 0 firmware code to operate the master die and the first slave die to boot the system and start up the platform.

Abstract: A multi-chip system and a data transmission method thereof are provided. The multi-chip system includes a first chip, a link unit, and a second chip. The first chip includes multiple transmitter (TX) channels and a first data processing module. The TX channels are configured to provide at least one transaction information. The first data processing module converts the at least one transaction information into at least one first data packet according to a general packet format and packs the at least one first data packet according to a specific packet format to generate a second data packet. The first data processing module merges two sets of second data packets into a third data packet and transmits the third data packet to the link unit. The second chip receives the third data packet through the link unit.

Abstract: An electronic assembly is provided, including a wiring board, a control element, and a pair of first internal electrical connectors. The wiring board includes a mounting surface, a first patterned conductive layer, a plurality of second patterned conductive layers, a plurality of near conductive holes, a plurality of far conductive holes, and a first conductive path. The first patterned conductive layer is located between the mounting surface and the second patterned conductive layers. The control element is mounted on the mounting surface of the wiring board. The pair of first internal electrical connectors are mounted on the mounting surface of the wiring board, and are adapted for mounting a pair of memory modules. The first conductive path extends from the control element at least through the corresponding second patterned conductive layer and the first patterned conductive layer to the pair of first internal electrical connectors.

Abstract: A host interconnection device includes a serializing module, an analysis module, an arbitration module, a data-writing tracking module, and a data-reading tracking module. The serializing module serializes at least one first read/write request generated by at least one processing module and a second read/write request generated by a chipset module, and outputs the first read/write request or the second read/write request. The analysis module generates analysis information according to the first read/write request or the second read/write request. The arbitration module arbitrates the analysis information and snoop information, and generates arbitration information. The data-writing tracking module performs a data-writing tracking operation on the arbitration information to generate a first snoop request, a data-writing indication, and a data-writing request.

Abstract: An output stage circuit comprising a bias voltage generator, a first amplifier circuit and a second amplifier circuit is provided. The bias voltage generator is coupled to an output terminal of the output stage circuit to generate a bias voltage according to an output voltage of the output terminal. The first amplifier circuit is coupled to the output terminal, a first power supply terminal and the bias voltage generator, receives a first pre-driving signal, a first predetermined voltage and the bias voltage, and determines whether to transmit a first voltage to serve as the output voltage. The second amplifier circuit is coupled to the output terminal, a second power supply terminal and the bias voltage generator, receives a second pre-driving signal, a second predetermined voltage and the bias voltage, and determines whether to transmit a second voltage to serve as the output voltage.

Abstract: An oscillator circuit comprises differential amplifiers connected in series and an auxiliary start circuit. A first output terminal and a second output terminal of each differential amplifier are respectively coupled to a first input terminal and a second input terminal of the next differential amplifier. Said first output terminal of the last differential amplifier is coupled to said second input terminal of the first differential amplifier. Said second output terminal of said last differential amplifier is coupled to said first input terminal of said first differential amplifiers. Said auxiliary start circuit generates a first disturbance signal and a second disturbance signal to said first input terminal and said second input terminal of a second differential amplifier according to said signal state of said first input terminal of a first differential amplifier. Said first different amplifier is one of said differential amplifiers. Said second differential amplifier is another differential amplifier.