Abstract: A microprocessor is shown, in which a branch predictor and an instruction cache are decoupled by a fetch-target queue (FTQ). The branch predictor performs branch prediction for N instruction addresses in parallel in the same cycle, wherein N is an integer greater than 1. In the current cycle, the branch predictor finishes branch prediction for N instruction addresses in parallel and, among the N instruction addresses with finished branch prediction, those that are not bypassed and do not overlap previously-predicted instruction addresses are pushed into the fetch-target queue, to be read out later as an instruction-fetching address for the instruction cache. The previously-predicted instruction addresses are pushed into the fetch-target queue in a previous cycle.

Abstract: A data processing method includes the following steps: a processor receives a symmetric wrapping key, and when an application needs to use a user private key, the processor executes an encryption and decryption instruction in a hardware-acceleration instruction-set. The encryption and decryption instruction is configured to apply the symmetric wrapping key to decrypt a wrapped private key that corresponds to the application to obtain the user private key. In addition, the symmetric wrapping key is stored in a model specific register of the processor.

Abstract: A multi-chip system and a data transmission method thereof are provided. The multi-chip system includes a first chip, a link unit, and a second chip. The first chip includes multiple transmitter (TX) channels and a first data processing module. The TX channels are configured to provide at least one transaction information. The first data processing module converts the at least one transaction information into at least one first data packet according to a general packet format and packs the at least one first data packet according to a specific packet format to generate a second data packet. The first data processing module merges two sets of second data packets into a third data packet and transmits the third data packet to the link unit. The second chip receives the third data packet through the link unit.

Abstract: A microprocessor with a multistep-ahead branch predictor is shown. The branch predictor is coupled to an instruction cache and has an N-stage pipelined architecture, which is configured to perform branch prediction to control the instruction fetching of the instruction cache. The branch predictor performs branch prediction for (N?1) instruction-address blocks in parallel, wherein the (N?1) instruction-address blocks include a starting instruction-address block and (N?2) subsequent instruction-address blocks. The branch predictor is thereby ahead of branch prediction of the starting instruction-address block. The branch predictor stores reference information about branch prediction in at least one memory and performs a parallel search of the memory for the branch prediction of the (N-1) instruction-address blocks.

Abstract: An instruction simulation device and a method thereof are provided. The simulation device includes a monitor, which is configured to determine whether a ready-for-execution instruction is an instruction under a new/extended instruction set sharing the same instruction set architecture as that of the processor. If the ready-for-execution instruction is an extended instruction, it is converted into a simulation program which consists of a compatible instruction sequence further composed of at least one native instruction of the processor or a compatible instruction recognizable/executable by the processor. An execution result of the extended instruction is simulated by executing the simulation program, thereby extending the service life of an electronic appliance embodied with the disclosed simulation device therein.

Abstract: The disclosure relates to an instruction conversion device, an instruction conversion method, an instruction conversion system, and a processor. The instruction conversion device includes a monitor for determining whether a ready-for-execution instruction is an instruction that belongs to a new instruction set or an extended instruction set, wherein the new instruction set and the extended instruction set have the same type of the instruction set architecture as that of the processor. If the ready-for-execution instruction is determined as an extended instruction, this extended instruction is converted into a converted instruction sequence by means of the conversion system, this converted instruction sequence is then sent to the processor for executions, thereby extending the lifespans of the electronic devices embodied with old-version processors.

Abstract: Microcode combination of complex instructions is shown. A microprocessor includes an instruction queue, an instruction decoder, and a microcode controller. The instruction decoder is coupled to the instruction queue. The microcode controller is coupled to the instruction decoder and has a memory. The memory stores a combined microcode for M complex instructions arranged in a specific order, where M is an integer greater than 1. When the M complex instructions in the specific order have popped out of the first to M-th entries of the instruction queue, the instruction decoder operates the microcode controller to read the memory for the combined microcode with microcode reading trapping happened just once.

Abstract: A microprocessor with a solution to instruction fetching failure is shown. The branch predictor and the instruction cache are decoupled by a fetch target queue. In response to instruction fetching failure of a target fetching address, the instruction cache regains the target fetching address from the fetch target queue to restart the failed instruction fetching.

Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a pair of first contacts and eight second contacts. The pair of first contacts is a pair of differential signal contacts. The second contacts are arranged around the pair of first contacts. Two of the second contacts are arranged along a straight line perpendicular to a connecting line of the pair of first contacts. The position distribution and electrical properties of the other six of the second contacts are symmetrical to each other relative to the straight line.

Abstract: An acceleration technology for accessing system memory, which provides translation agent hardware that calculates the physical address of the system memory based on an access request issued from the device end. The translation agent hardware has a cache memory that stores information to speed up the calculation of the physical address. Each cache line corresponds to a last-recently used (LRU) index value, and the cache line with the greatest LRU index value is preferentially released to be reassigned. A counter counts a count value to show an isochronous caching demand. LRU index values of cache lines assigned to non-isochronous caching are kept not lower than the count value, and thereby isochronous caching takes precedence over non-isochronous caching.

Abstract: A processor and an operating method thereof are provided. The processor comprises a plurality of physical registers and a renaming circuit. The renaming circuit is coupled to the plurality of physical registers and is configured to receive an instruction sequence and check the instruction sequence. When a current instruction of the instruction sequence comprises a move instruction, the renaming circuit assigns a first physical register, which is assigned to a source logical register of the current instruction previously, to a destination logical register of the current instruction. The first physical register is one of the plurality of physical registers.

Abstract: A multi-chip system and a cache processing method are provided. The multi-chip system includes multiple chips. Each chip includes multiple clusters, a crossbar interface, and a snoop system. Each cluster corresponds to a local cache. The crossbar interface is coupled to the clusters and a crossbar interface of another chip. The snoop system is coupled to the crossbar interface and performs unidirectional transmission with the crossbar interface. The snoop system includes a snoop table module and multiple trackers. The snoop table module includes a shared cache, which records a snoop table. Multiple trackers are coupled to the snoop table module, query the snoop table in the shared cache according to a memory access request initiated by one of clusters, and update the snoop table according to a query result. The snoop table corresponds to a storage structure of the local cache corresponding to the clusters in all chips.

Abstract: An electronic assembly is provided, including a wiring board, a control element, and a pair of first internal electrical connectors. The wiring board includes a mounting surface, a first patterned conductive layer, a plurality of second patterned conductive layers, a plurality of near conductive holes, a plurality of far conductive holes, and a first conductive path. The first patterned conductive layer is located between the mounting surface and the second patterned conductive layers. The control element is mounted on the mounting surface of the wiring board. The pair of first internal electrical connectors are mounted on the mounting surface of the wiring board, and are adapted for mounting a pair of memory modules. The first conductive path extends from the control element at least through the corresponding second patterned conductive layer and the first patterned conductive layer to the pair of first internal electrical connectors.

Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a first contact and six second contacts. The second contacts are arranged around the first contact. When the first contact is a power contact or a ground contact, the second contacts are signal contacts. When the first contact is a signal contact, three of the second contacts are power contacts or ground contacts and are not adjacent to each other.

Abstract: A circuit, including a TAP circuit, a routing circuit, a first test path and a second test path, is provided. A first input terminal and a first output terminal of the routing circuit are respectively coupled to a scan output terminal and a first scan input terminal of the TAP circuit. A first terminal of the first test path is coupled to a second input terminal of the routing circuit. A second terminal of the first test path is coupled to a second output terminal of the routing circuit. A first terminal of the second test path is coupled to a third input terminal of the routing circuit. A second terminal of the second test path is coupled to a third output terminal of the routing circuit. The routing circuit couples the scan output terminal of the TAP circuit to the first scan input terminal of the TAP circuit or the first terminal of the first test path or the first terminal of the second test path.

Abstract: A processing system includes at least one core, at least one accelerator function unit (AFU), a microcontroller, and a memory access unit. The AFU and the core share a plurality of virtual addresses to access a memory. The microcontroller is coupled between the core and the AFU. The core develops and stores a task in one of the virtual addresses. The microcontroller analyzes the task and dispatches the task to the AFU. The AFU accesses the virtual address indicating where the task is stored through the memory access unit to executes the task.

Abstract: The disclosure provides a data prefetching auxiliary circuit, a data prefetching method, and a microprocessor. The data prefetching auxiliary circuit includes a stride calculating circuit, a comparing module, a stride selecting module, and a prefetching output module. The stride calculating circuit receives an access address to calculate and provide a stride. The comparing module receives the access address and the stride, generates a reference address based on a first multiple, the access address and the stride, determines whether the reference address matches any of a plurality of history access addresses, and generates and outputs a hit indicating bit value. The stride selecting module receives the hit indicating bit value, and determines whether to output the hit indicating bit value based on a prefetch enabling bit value. The prefetching output module determines a prefetch address according to the output of the stride selecting module.

Abstract: A method for designing a power network is provided and includes: initializing via widths and power-trace widths; determining whether utilization rates of first, second and third routing tracks are respectively equal to first, second and third values; when said utilization rate of said first routing tracks is not equal to said first value, adjusting said distance between first and second power traces until said utilization rate thereof is equal to said first value; when said utilization rate of said second routing tracks is not equal to said second value, adjusting said distance between third and fourth power traces until said utilization rate thereof is equal to said second value; and when said utilization rate of said third routing tracks is not equal to said third value, adjusting said distance between fifth and sixth power traces until said utilization rate thereof is equal to said third value.

Abstract: A processing system includes at least one core, at least one accelerator function unit (AFU) and an acceleration interface. The unit runs a plurality of processes and develops at least one task queue corresponding to each of the processes. The core generates several command packets and pushes them into the corresponding task queue. The AFU are used to execute the command packets. The acceleration interface is arranged between the AFU and the core to receive an acceleration interface instruction from the processing core, and establish a bit map based on the acceleration interface instruction. The bit map is used to indicate which task queue contains the command packets that have been generated.

Abstract: A circuit, including a TAP circuit, a routing circuit, a first test path and a second test path, is provided. A first input terminal and a first output terminal of the routing circuit are respectively coupled to a scan output terminal and a first scan input terminal of the TAP circuit. A first terminal of the first test path is coupled to a second input terminal of the routing circuit. A second terminal of the first test path is coupled to a second output terminal of the routing circuit. A first terminal of the second test path is coupled to a third input terminal of the routing circuit. A second terminal of the second test path is coupled to a third output terminal of the routing circuit. The routing circuit couples the scan output terminal of the TAP circuit to the first scan input terminal of the TAP circuit or the first terminal of the first test path or the first terminal of the second test path.