Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.

Abstract: An electronic chip includes a shared strip with first and second spaced apart portions extending along a direction of elongation and an intermediate connecting portion extending between the first and second portions. The second portion is connected to a pad that has a greater surface area than the second portion. The first portion is formed by a first plurality of metallic strips. Metallic strips of the first plurality of metallic strips that are adjacent and side by side are separated by a distance smaller than a width of those metallic strips. The second portion is formed by a second plurality of metallic strips. Metallic strips of the second plurality of metallic strips that are adjacent and side by side are separated by a distance smaller than a width of those metallic strips.

Abstract: An interconnection substrate includes a thermomechanical support crossed by at least one electric interconnection hole. A first interconnection network is formed on a first surface of the thermomechanical support and a second interconnection network is formed on a second surface of the thermomechanical support. Each interconnection network includes and interconnection level formed by at least one metal track from which at least one metal via extends. The at least one metal track and the at least one metal via are embedded in an insulator layer so that the at least one metal via is flush with a surface of the insulator layer most distant from the thermomechanical support. At least one metal track protrudes from the insulator layer of the last interconnection level. The metal vias are configured to electrically couple together two adjacent levels and/or the last level with the at least one protruding metal track.

Abstract: A register bank of a channel of a direct memory access circuit is initialized. Transfer cycles are executed as configured by the register bank, and updates are made to the registers from a memory. At each transfer cycle, an operation is performed in accordance with a first field of the register bank to either: carry on the execution or generate a first signal and suspend the execution. In response to each reception of the first signal by a central processing unit, an operation is performed to either: generate a second signal or modify the content of the register band and/or record into the memory a first item representative of a next update of the register bank. A second signal is then generated.

Abstract: An embodiment level converter circuit is configured to receive, as a current supply, a current proportional to temperature.

Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.

Abstract: The image sensor includes an array of photosensitive pixels comprising at least two sets of at least one pixel, control circuit configured to generate at least two different timing signals and adapted to control an acquisition of an incident optical signal by the pixels of the array, and distribution circuit configured to respectively distribute said at least two different timing signals in said at least two sets of at least one sensor, during the same acquisition of the incident optical signal.

Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator configured to compare a first voltage with a threshold, the first voltage being equal, during a first period, to a first increasing ramp and, during a second period, to a second decreasing ramp, the threshold having a first value during the first period and a second value during the second period, the first and second values being variable.

Abstract: In an embodiment, a voltage converter includes: a first transistor coupled between a first rail configured to receive a supply voltage and a first node; and an inductance coupled between the first node and a second node configured to deliver an output voltage, wherein, at each operating cycle of the converter, the first transistor is maintained in the on state for a first time period proportional to the inverse of a voltage difference between the supply voltage and the output voltage.

Abstract: An embodiment voltage converter includes a first transistor and a second transistor coupled in series, and a first circuit configured to control the first and second transistors. The control terminal of the second transistor is coupled to a first output of the first circuit by a second circuit configured to delay the control signals supplied at the first output by a first duration. The control terminal of the first transistor is coupled to a second output of the first circuit by a circuit configured to delay the control signals supplied at the second output, for a second period of each operating cycle, by a duration equal to twice the first duration and, during a second period of each operating cycle, by a duration equal to the first duration.

Abstract: An optoelectronic element is located in a package. The package includes a first optical block and a second optical block that are attached to each other by a bonding layer. One of the first and second optical blocks is attached to lateral walls of the package by glue. The material of the bonding layer is configured to induce less stress to the first and second optical blocks than the glue.

Abstract: An ambient light sensor includes pixels arranged in an array. Each pixel includes a doped insulated well of a first type, a pinned photodiode in the well, a doped region of a second type arranged in the well, a transfer gate coupling the photodiode to said region, and a first circuit applying a first or second potential to the well. A successive approximation analog-to-digital converter of the sensor has a node connected to the doped regions of the pixels, a switch applying a third potential to the node, a comparator coupled to the node, and a second circuit receiving an output of the comparator and controlling the first circuits to selectively apply the first and second potentials. A sensor control circuit controls the gates and the first switch.

Abstract: A time-of-flight sensor includes a first light ray generation circuit and a second light ray reception circuit. A resin layer encapsulates the first light ray generation circuit and the second light ray reception circuit. A first region configured to emit light rays of the first light ray generation circuit is exposed at a surface of the resin layer. A second region configured to receive light rays of the second light ray reception circuit is also exposed at that surface of the resin layer. The surface of the resin layer is configured to be directed towards a scene.

Abstract: An imaging device includes a first layer made of quantum dots and a second layer including at least two filter regions extending over the first layer. The at least two filter regions are configured to transmit distinct wavelengths. The quantum dots of the first layer are configured to generate charges upon reception of light in the distinct wavelengths.

Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

Abstract: A carrier substrate is configured to carry at least one electronic chip and includes a mounting front face. An encapsulating cover is mounted on the front face of the carrier substrate through a mounting. This mounting includes at least one seating surface through which the cover and the carrier substrate make contact. At least one adhesive bead is located elsewhere than the seating surface in order to securely fasten the encapsulation cover and the carrier substrate.

Abstract: Described herein is a time-of-flight ranging system and methods for its operation. The system includes an array of single photon avalanche diode (SPAD) pixels and control circuitry. The control circuitry simultaneously accumulates integrated SPAD event data from one cluster of SPAD pixels while integrating SPAD event data from another cluster during different target illuminations. The system also includes first and second VCSEL clusters, each responsible for a different target illumination. By processing and managing the data in this manner, the system can effectively reduce the time used to gather and analyze the event data, leading to faster and more accurate distance measurements.

Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

Abstract: According to one aspect, an ambient-light sensor includes a photodiode configured to generate an electrical signal according to an ambient light, a capacitive-feedback transimpedance amplifier connected at its input to the photodiode for receiving a signal generated by the photodiode and for generating as an output an amplified signal from the signal generated by the photodiode, and an auto-zero switch at the input of the capacitive-feedback transimpedance amplifier. The ambient-light sensor further includes a control circuit including a bootstrap circuit configured to receive an initial positive- or zero-voltage logic control signal, and then generate, from this initial logic control signal, an adapted logic control signal having a first positive voltage level and a second negative voltage control level for controlling the auto-zero switch.

Abstract: In an embodiment an electronic device includes a first MOS-type transistor and a second MOS-type transistor connected as current mirrors, wherein the first transistor is diode connected and a first circuit configured to provide a first current equal to a first gate current of the first transistor multiplied by a size ratio of the first and second transistors.