Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

Abstract: According to one aspect, an ambient-light sensor includes a photodiode configured to generate an electrical signal according to an ambient light, a capacitive-feedback transimpedance amplifier connected at its input to the photodiode for receiving a signal generated by the photodiode and for generating as an output an amplified signal from the signal generated by the photodiode, and an auto-zero switch at the input of the capacitive-feedback transimpedance amplifier. The ambient-light sensor further includes a control circuit including a bootstrap circuit configured to receive an initial positive- or zero-voltage logic control signal, and then generate, from this initial logic control signal, an adapted logic control signal having a first positive voltage level and a second negative voltage control level for controlling the auto-zero switch.

Abstract: In an embodiment an electronic device includes a first MOS-type transistor and a second MOS-type transistor connected as current mirrors, wherein the first transistor is diode connected and a first circuit configured to provide a first current equal to a first gate current of the first transistor multiplied by a size ratio of the first and second transistors.

Abstract: The present disclosure is directed to a light-signal communication receiver device including a photo-receiving diode configured to generate a current signal on a first node from a received light signal, a preamplifier configured to convert the current signal on the first node into a voltage signal on a second node, and a differential amplifier including a first input connected to the first node and a second input connected to a third node coupled to the second node via an adjustment circuit. The adjustment circuit is configured to offset the level of the voltage signal of the second node, on the third node, in a controlled manner by a control signal.

Abstract: A device includes an application processor and a hardware signal processor coupled to the application processor. The hardware signal processor, in operation: receives a command pre-list during an initialization phase of the hardware signal processor, the command pre-list including a plurality of function describers, each of the plurality of function describers being associated with a respective plurality of parameter describers; generates a command list based on the command pre-list during the initialization phase; and stores the command list in memory circuitry.

Abstract: An embodiment of the present disclosure relates to a power supply interface comprising: a converter delivering a first DC voltage; a resistor connected between the converter and an output terminal of the interface delivering a second DC voltage; a first circuit delivering a second signal representative of a difference between the second DC voltage and a voltage threshold when a first signal is in a first state, and at a default value otherwise; a second circuit delivering a third signal representative of a value of a current in first resistor multiplied by a gain of the third circuit, and modifying the gain based on the second signal; and a third circuit configured to deliver a signal for controlling the converter based at least on the third signal.

Abstract: A near-field communication device operates to transmit data by near-field communications techniques to another device. The near-field communication device includes a memory that stores a message to be transmitted in an ASCII format. The message is retrieved from the memory and transmitted using the near-field communications techniques in an ASCII format.

Abstract: A first terminal receives a first DC voltage. A switch selectively couples the first terminal to a second terminal providing an output. A control circuit selectively actuates the switch in response to a comparison of the first DC voltage to a second DC voltage. A low-dropout (LDO) linear voltage regulator, connected between the first and third terminals, operates to provide the second DC voltage from the first DC voltage.

Abstract: An integrated circuit chip carrier includes a wall surrounding a cavity. The wall includes one or more levels where each level is formed from a layer of a resin around a block. The block is made of a material different from the resin. The block is removed to open the cavity.

Abstract: A unique hardware key is recorded a secure hardware environment. A first logic circuit of the secure hardware environment is configured to generate a unique derived key from said unique hardware key and at least one piece of information. The at least one piece of information relates to one or more of an execution context and a use of a secret key. The secure hardware environment further includes a first encryption device that performs a symmetric encryption of the secret key using the unique derived key. This symmetric encryption generates an encrypted secret key for use outside of the secure hardware environment.

Abstract: A cover for an electronic package is manufactured by placing an optical insert, having opposite faces and configured to allow light radiation to pass therethrough, between two opposite faces of a cavity of a mold in a position such that said optical faces of the optical insert make contact with said opposite faces of the cavity of the mold. A coating material is injected into the cavity and around the optical insert. The coating material is set to obtain a substrate that is overmolded around the optical insert so as to produce the cover. An electronic package includes an electronic chip mounted to a support substrate with the cover formed by the overmolded substrate mounted to the support substrate.

Abstract: An electronic device includes a carrier substrate having a front face. An electronic chip is mounted on the front face of the carrier substrate and includes an optical component. An encapsulation cover is mounted on top of the front face of the carrier substrate and bounds a chamber within which the chip is situated. A front opening extends through the cover and is situated in front of the optical component. An optical element, designed to allow light to pass, is mounted within the chamber at a position which covers the front opening of the encapsulation cover. The optical element includes a central region designed to deviate the light and having an optical axis aligned with the front opening and the optical component. A positioning pattern is provided on the optical element to assist with mounting the optical element to the cover and mounting the cover to the carrier substrate.

Abstract: The present disclosure relates to an assembly for an electronic device, the assembly comprising: a display screen comprising a plurality of pixels arranged in a matrix scheme comprising rows orientated in a first direction and columns orientated in a second direction; and a proximity sensor comprising at least one optical light emitter, each adapted to emit a light beam through one or more first pixels of the display screen, and an optical detector adapted to receive through one or more second pixels of the display screen the light beam emitted by the at least one optical light emitter and reflected on an object; wherein none of the one or more second pixels is in the same row as any of the one or more first pixels, and none of the one or more second pixels is in the same column as any of the one or more first pixels.

Abstract: An integrated circuit device includes at least one inductive component with at least one integrated metal winding that is at least partially embedded in a coating. The coating includes at least one ferromagnetic material. The coating optionally includes a non-magnetic material, for example a dielectric.

Abstract: An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block.

Abstract: An apparatus is for testing a device to be supplied with power via USB Power Delivery (USB-PD). The apparatus includes at least one USB Type-C connector configured to be connected to the device to be supplied with power to be tested, the at least one USB Type-C connector including a power supply terminal. Processing circuitry of the apparatus is configured to verify that a voltage at the power supply terminal is lower than a first threshold, verify a role of the device, generate requests representative of power supply configurations supported by the role of the device, and verify compatibility of the power supply configurations supported by the device with standardized power supply configurations.

Abstract: An apparatus is adapted to test a power supply device of the USB-PD type which includes at least one USB Type-C connector. The USB Type-C connector is intended to be connected to the power supply device to be tested. The device is separate from the apparatus.

Abstract: An avalanche photodiode includes a stack of layers. The stack of layers includes an avalanche diode (of PN or PIN type) and a layer having quantum dots located therein. The stack of layers further includes: a charge extraction layer over the layer which includes quantum dots; a transparent conducting layer over the charge extraction layer; and an insulating layer over the transparent conducting layer. The quantum dots includes ligands formed by molecules of dopants.

Abstract: A heat dissipation device includes a substrate with a network of thermally-conductive vias and thermally-conductive layers. The substrate has a first surface and a second surface opposite to the first surface. A heat dissipation interface layer including a stack of a first layer made of a first thermally-conductive material and a second layer made of a second thermally-conductive material. The first material is different from the second material. A surface of the first layer is coplanar with the first surface of the substrate. At least one of the thermally-conductive vias of said network supports and is in contact with the first layer. At least one opening thoroughly crosses the stack of the first and second layers. Material of the substrate fills the opening in the first layer.

Abstract: A device for assembling at least two shots of a scene acquired by at least one sensor includes a memory and processing circuitry. The processing circuitry is configured to save, in the memory, a first data set contained in a first signal generated by each pixel of the sensor and indicative of a first shot of the scene, and a second data set contained in a second signal generated by each pixel of the sensor and indicative of a second shot of the scene. The processing circuitry is further configured to assemble the first and second shots on the basis of the content of the first and second data sets of a plurality of pixels in order to form a resulting scene.