Patents Assigned to Sumitomo Electric Device Innovations, Inc.
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Publication number: 20230282417Abstract: A capacitor according to an embodiment of the present disclosure includes a substrate, a first electrode disposed on the substrate, a dielectric film disposed on the first electrode, a second electrode disposed on the dielectric film, a third electrode in contact with the second electrode in a first region of at least a portion of a lower surface of the third electrode, and an organic insulator film covering an upper portion of the dielectric film, an upper portion of the second electrode, and the third electrode. In a normal direction normal to an upper surface of the substrate, the organic insulator film is not disposed between the lower surface of the third electrode and the second electrode.Type: ApplicationFiled: March 1, 2023Publication date: September 7, 2023Applicant: Sumitomo Electric Device Innovations, Inc.Inventors: Takeshi IGARASHI, Yoshihide KOMATSU
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Publication number: 20230282686Abstract: A capacitor includes a substrate, a first electrode provided on the substrate, a dielectric film provided on the first electrode, a second electrode provided on the dielectric film and having an outer periphery positioned inside the outer periphery of the first electrode in a plan view viewed from above in a direction normal to an upper surface of the substrate, a third electrode that is in contact with the second electrode in a region inside the second electrode in the plan view, is separated upward from the first electrode and the dielectric film outside the region in the plan view, and has an outer periphery positioned inside the outer periphery of the first electrode and an outer periphery of the dielectric film in the plan view, and a protective film covering the second electrode and the third electrode and being in contact with the second electrode and the third electrode.Type: ApplicationFiled: February 13, 2023Publication date: September 7, 2023Applicant: Sumitomo Electric Device Innovations, Inc.Inventor: Yasuyo YOTSUDA
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Publication number: 20230268343Abstract: A semiconductor device includes a source bus bar provided on a first surface of a substrate and overlapping with a first via hole penetrating through the substrate, a plurality of first transistors arranged in a second direction intersecting a first direction, each of the first transistors including a first source finger, a first drain finger and a first gate finger which extend in the first direction on the first surface, the first source finger being electrically connected to the source bus bar, and a plurality of second transistors arranged in the second direction, each of the second transistors including a second source finger, a second drain finger and a second gate finger which extend in the first direction on the first surface, the second source finger being electrically connected to the source bus bar, the first transistors and the second transistors sandwiching the source bus bar.Type: ApplicationFiled: February 22, 2023Publication date: August 24, 2023Applicant: Sumitomo Electric Device Innovations, Inc.Inventors: James WONG, Kento KAWASAKI
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Patent number: 11736335Abstract: Various embodiments of the present disclosure relate to transmitter systems, methods, and instructions for signal predistortion.Type: GrantFiled: December 6, 2021Date of Patent: August 22, 2023Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Ruikang Yang, Michael Russo, Simon Hamparian
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Publication number: 20230258889Abstract: An optical device according to one embodiment includes an optical element, a sleeve including a receptacle portion and an insertion portion, and a base having a lower plate having a main surface with the optical element being mounted thereon and a side wall having a hole with the insertion portion of the sleeve optically coupled with the optical element inserted into the hole. A step difference at a position lower than the main surface is formed at a lower position of the hole in the side wall.Type: ApplicationFiled: June 11, 2021Publication date: August 17, 2023Applicants: Sumitomo Electric Device Innovations, Inc., Sumitomo Electric Industries, Ltd.Inventors: Kazushige OKI, Satoshi YOSHIMURA, Kuniyuki ISHII, Masanobu KAWAMURA
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Patent number: 11710719Abstract: A method for manufacturing an electronic component includes preparing a mounting substrate provided with a first region to mount an electronic component thereon and a second region having conductivity, covering the second region with resin, applying a metal paste on the first region, mounting the electronic component on the first region with the metal paste, and removing the resin covering the second region. The mounting includes heating the mounting substrate to cure the metal paste with the electronic components being placed on the metal paste applied on the first region. The resin peeled from the second region by the heating is removed in the removing.Type: GrantFiled: June 8, 2020Date of Patent: July 25, 2023Assignee: Sumitomo Electric Device Innovations, Inc.Inventor: Taketo Kawano
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Publication number: 20230230904Abstract: A semiconductor device includes a base having a first surface on which the semiconductor element is mounted and a second surface opposite to the first surface, a first edge portion having a step from the first surface toward the second surface in a first region of a peripheral edge of the base, a first terminal that is arranged at a position facing the first edge portion when viewed from a thickness direction of the base, a conductive member for electrically connecting the semiconductor element and the first terminal to each other, and a resin material for sealing a part of the base, the semiconductor element, and a part of the first terminal.Type: ApplicationFiled: January 11, 2023Publication date: July 20, 2023Applicant: Sumitomo Electric Device Innovations, Inc.Inventor: Akihiro SHINSAI
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Publication number: 20230221505Abstract: An optical device according to one embodiment includes: a light-emitting element; first and second lenses optically coupled with the light-emitting element; an optical component provided between the light-emitting element and the second lens, optically coupling each of the light-emitting element and the second lens, and multiplexing input lights; and a base having a lower plate having a plurality of convex mounting surfaces with each of the light-emitting element, the first lens, the second lens, and the optical component being mounted thereon and a side wall with a receptacle being connected thereto.Type: ApplicationFiled: June 11, 2021Publication date: July 13, 2023Applicants: Sumitomo Electric Device Innovations, Inc., Sumitomo Electric Industries, Ltd.Inventors: Kazushige OKI, Kazunobu KOBAYASHI, Hiroshi HARA, Eiji TSUMURA, Masanobu KAWAMURA, Satoshi YOSHIMURA, Kuniyuki ISHII, Fumihiro NAKAJIMA, Hideaki KITAJIMA, Hideaki KAMISUGI
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Publication number: 20230213047Abstract: An optical transceiver includes an outer part provided outside the apparatus upon an engagement of the optical transceiver with the apparatus. The outer part includes a first spindle, a rotational member, a sliding member. The rotational member is configured to rotate on the first spindle. The sliding member is configured to move along the first direction. The rotational member has a hole. The sliding member has a second spindle. The first spindle and the second spindle are fit with the hole. The optical transceiver includes an inner part provided inside the apparatus upon the engagement with the apparatus. The hole has a first circular area, a second circular area, and a straight area. The first spindle is fit with the first circular area. The second spindle is fit with the second circular area. The straight area is connected between the first circular area and the second circular area.Type: ApplicationFiled: December 28, 2022Publication date: July 6, 2023Applicant: Sumitomo Electric Device Innovations, Inc.Inventor: Masato HINO
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Patent number: 11688773Abstract: Disclosure is a method for manufacturing a semiconductor device. The method includes forming a source electrode and a drain electrode on a nitride semiconductor layer formed on a main surface of a SiC substrate, forming a gate electrode having a laminated structure including a Ni layer and an Au layer on the Ni layer between the source electrode and the drain electrode on the nitride semiconductor layer and forming a first metal film having the same laminated structure as the gate electrode in a region adjacent to the source electrode with an interval therebetween, forming a second metal film to contact with the source electrode and the first metal film, forming a hole being continuous with the first metal film from a back surface of the SiC substrate, and forming a metal via being continuous with the first metal film from the back surface in the hole.Type: GrantFiled: February 14, 2020Date of Patent: June 27, 2023Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Shunsuke Kurachi, Tsutomu Komatani
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Publication number: 20230197628Abstract: A method for manufacturing a semiconductor device includes selectively forming an insulating film on a region of a substrate serving as a scribe line; and forming a first semiconductor layer in a state where a cavity is provided on the insulating film. The cavity is buried in the first semiconductor layer.Type: ApplicationFiled: February 21, 2023Publication date: June 22, 2023Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Tadahiro HACHUDA
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Publication number: 20230198169Abstract: A semiconductor device includes a base, a matching circuit including a substrate, a ground layer, and a signal line, wherein a width of the signal line on a first end side of the substrate is smaller than a width of the substrate and larger than that of the signal line on a second end side, and a distance between the ground layer and the signal line on the first end side is larger than a distance therebetween on the second end side, a semiconductor element electrically connected to the signal line on the first end side of the matching circuit by first bonding wires, a frame body, a feedthrough having a lead, and second bonding wires electrically connected to the lead and the signal line on the second end side, wherein the first bonding wires are arranged in parallel, and the second bonding wires are arranged in parallel.Type: ApplicationFiled: May 12, 2021Publication date: June 22, 2023Applicant: Sumitomo Electric Device Innovations, Inc.Inventor: Ikuo NAKASHIMA
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Publication number: 20230188218Abstract: An optical transmitter includes: a controller that generates a multi-level amplitude modulated signal based on transmission data that is binary data; a driver that generates a drive signal in accordance with the multi-level amplitude modulated signal; and a light emitter that generates an optical signal in accordance with the drive signal. The controller selects one of a first encoding method and a second encoding method in accordance with a switching signal. The controller generates the multi-level amplitude modulated signal by converting a bit string of M (M is an integer of 2 or more) bits included in the transmission data into a pulse signal having 2M logic levels using a selected encoding method. The controller sets voltage values of the 2M logic levels depending on the selected encoding method.Type: ApplicationFiled: June 7, 2021Publication date: June 15, 2023Applicant: Sumitomo Electric Device Innovations, Inc.Inventor: Shinta KASAI
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Publication number: 20230179466Abstract: Various embodiments of the present disclosure relate to transmitter systems, methods, and instructions for signal predistortion.Type: ApplicationFiled: December 6, 2021Publication date: June 8, 2023Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Ruikang YANG, Michael RUSSO, Simon HAMPARIAN
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Publication number: 20230179467Abstract: Various embodiments of the present disclosure relate to transmitter systems, methods, and instructions for signal predistortion. The transmitter system includes an intermodulation distortion (IMD) filter module configured to filter a detected feedback signal (Yin) to generate a targeted filtered signal (Yout), a digital pre-distortion (DPD) coefficient estimation module configured to update signal generation coefficients based on comparing an input signal (Sin) with the targeted filtered signal (Yout), and a distortion compensation processing module configured to generate a pre-distorted signal (Uout) based on the input signal (Sin) using the updated signal generation coefficients.Type: ApplicationFiled: December 6, 2021Publication date: June 8, 2023Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Ruikang YANG, Michael RUSSO, Simon HAMPARIAN
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Publication number: 20230179468Abstract: Various embodiments of the present disclosure relate to transmitter systems, methods, and instructions for signal predistortion. The transmitter system includes a primary digital predistortion (DPD) layer and a secondary DPD layer. The primary DPD layer includes a DPD coefficient estimation module configured to update primary signal generation coefficients based on comparing a secondary predistorted signal (Uout) with a detected feedback signal (Yout), and a primary distortion compensation processing module configured to generate a primary predistorted signal (Uout?) based on the secondary predistorted signal (Uout) using the updated primary signal generation coefficients.Type: ApplicationFiled: December 6, 2021Publication date: June 8, 2023Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Ruikang YANG, Michael RUSSO, Simon HAMPARIAN
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Patent number: 11626323Abstract: A semiconductor device is made by: forming a metal film containing Al on a surface of a substrate product including a substrate and a nitride semiconductor layer on the substrate, the metal film covering a via hole forming predetermined region, and the surface of the substrate product being located on the nitride semiconductor layer side, forming an etching mask having an opening for exposing the via hole forming predetermined region on a back surface of the substrate product, the back surface of the substrate product being located on the substrate side, and forming a via hole in the substrate product by reactive ion etching, the via hole reaching the surface from the back surface and exposing the metal film. In the forming of the via hole, a reaction gas containing fluorine is used during a period at least including a termination of etching.Type: GrantFiled: February 16, 2021Date of Patent: April 11, 2023Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Toshiyuki Kosaka, Haruo Kawata
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Publication number: 20230107764Abstract: A semiconductor device includes: a package having a top surface and a bottom surface; a semiconductor element arranged in the package; and a base which is arranged in the package and on which the semiconductor element is mounted. A top surface of the base is exposed to the top surface of the package, and a bottom surface of the base is exposed to the bottom surface of the package.Type: ApplicationFiled: October 4, 2022Publication date: April 6, 2023Applicant: Sumitomo Electric Device Innovations, Inc.Inventor: Akira SAHASHI
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Publication number: 20230097270Abstract: A package for a semiconductor device includes a metal base plate, a wall portion, a first metal film, and a lead portion. The base plate has a first region and a second region surrounding the first region. The wall portion has a first frame body comprising metal and a second frame body comprising resin. The first frame body is provided on the second region. The second frame body is provided on the first frame body. The first metal film is provided on the second frame body. The lead portion is conductively bonded to the first metal film. The first frame body is conductively bonded to the base plate. A thickness of the first frame body in a first direction that is a direction in which the first frame body and the second frame body are arranged is larger than a thickness of the first metal film in the first direction.Type: ApplicationFiled: September 26, 2022Publication date: March 30, 2023Applicant: Sumitomo Electric Device Innovations, Inc.Inventor: Shingo INOUE
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Publication number: 20230102118Abstract: A semiconductor device includes a substrate having a front surface including a first long side and a second long side extending in a first direction and opposed to each other, and a first short side and a second short side extending in a second direction intersecting the first direction and opposed to each other, a source finger provided on the front surface, a drain finger provided on the front surface, and a gate finger provided on the front surface and sandwiched between the source finger and the drain finger, wherein a via hole penetrating the substrate is provided in the substrate, a region where the via hole is connected to the source finger in the front surface is contained within the source finger, and the via hole has a maximum width in the first direction larger than a maximum width in the second direction.Type: ApplicationFiled: September 14, 2022Publication date: March 30, 2023Applicant: Sumitomo Electric Device Innovations, Inc.Inventors: James WONG, Kento KAWASAKI