Patents Assigned to Sumitomo Electric Device Innovations, Inc.
  • Publication number: 20220157950
    Abstract: A semiconductor device includes a semiconductor layer, a source electrode and a drain electrode that are disposed on the upper surface of the semiconductor layer, a gate electrode disposed on the upper surface of the semiconductor layer and located between the source electrode and the drain electrode, a first insulating film disposed on the gate electrode, and a field plate disposed on the first insulating film, at least part of the field plate overlapping the gate electrode, the field plate including a first metal layer and a second metal layer disposed on the upper surface of the first metal layer, the first metal layer containing gold, the second metal layer containing at least one of tantalum, tungsten, molybdenum, niobium, and titanium.
    Type: Application
    Filed: November 8, 2021
    Publication date: May 19, 2022
    Applicant: Sumitomo Electric Device Innovations, Inc.
    Inventors: Yukinori NOSE, Kenichi WATANABE
  • Patent number: 11335816
    Abstract: A metal-insulator-metal (MIM) capacitor and a process of forming the same are disclosed. The process includes steps of: forming a lower electrode that provides a lower layer and an upper layer; forming an opening in the upper layer; forming a supplemental layer on the lower layer exposed in the opening; heat treating the lower electrode and the supplemental layer; covering at least the upper layer of the lower electrode with an insulating film; and forming an upper electrode in an area on the insulating film, where the area is not overlapped with the supplemental layer and within 100 ?m at most from the supplemental layer. A feature of the MIM capacitor is that the supplemental layer is made of a same metal as a metal contained in the lower layer of the lower electrode.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: May 17, 2022
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Yoshihide Komatsu
  • Publication number: 20220148985
    Abstract: A microwave circuit integrated on a common semiconductor substrate, includes: a first-stage amplifier to amplify an input high-frequency signal having a first frequency; a main-system amplification stage to amplify and output one signal having the first frequency branched from an output of the first-stage amplifier; a branch stage to generate a signal having double the frequency of the first frequency; and a sub-system amplification stage to amplify and output the signal having double the frequency. An amplification circuit constituting the first-stage amplifier, an amplification circuit included in the branch stage, an amplification circuit included in the main-system amplification stage, and an amplification circuit included in the sub-system amplification stage are connected in series between a power supply and ground in a DC manner, and each is a current reuse type amplifier including two-stage transistors connected in series between a signal input and a signal output in an AC manner.
    Type: Application
    Filed: January 21, 2022
    Publication date: May 12, 2022
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Kenshi NAITO
  • Patent number: 11303249
    Abstract: A consecutive Doherty amplifier is disclosed. The Doherty amplifier includes a carrier amplifier, a power splitter, a peak amplifier, and a phase compensator. The carrier amplifier receives a radio frequency signal with interposing any signal splitters. The power splitter splits an output of the carrier amplifier into first and second split signals. The phase compensator transfers the second split signal to the peak amplifier. The first split signal is combined with the output of the peak amplifier.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: April 12, 2022
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventors: Andrey Grebennikov, James Wong, Naoki Watanabe
  • Patent number: 11302817
    Abstract: A semiconductor device type of field effect transistor (FET) primarily made of nitride semiconductor materials is disclosed. The FET includes a nitride semiconductor stack providing primary and auxiliary active regions and an inactive region surrounding the active regions; electrodes of a source, a drain, and a gate; an insulating film covering the electrodes and the semiconductor stack; and a field plate on the insulating film. A feature of the FET of the invention is that the field plate is electrically in contact with the auxiliary active region through the opening provided in the insulating film.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: April 12, 2022
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Takuma Nakano
  • Publication number: 20220108931
    Abstract: A method for manufacturing a semiconductor device includes forming a lead frame assembly in which a first side wall portion and a second side wall portion, both made of a resin, are joined to each other in a state of having a metal lead frame sandwiched therebetween; applying a sintering metal paste to a disposition region of the lead frame assembly and disposing the lead frame assembly on the sintering metal paste; and sintering the sintering metal paste between a metal base of the semiconductor device and the lead frame assembly to join the base and the lead frame assembly to each other.
    Type: Application
    Filed: December 15, 2021
    Publication date: April 7, 2022
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Takashi KITAWADA
  • Patent number: 11282809
    Abstract: A method of manufacturing an electronic component having an electrode at an end portion thereof is disclosed. The method includes placing a jig on a heater block, wherein the jig includes a path inclined with respect to a pedestal including a placement surface and extending toward the pedestal; placing an electronic component main body having the electrode on the placement surface with the electrode facing the path; rolling a ball-shaped solder in the path to reach the electrode; and melting the solder through the pedestal to attach the molten solder to the electrode.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: March 22, 2022
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Yasuyuki Yamauchi
  • Patent number: 11283145
    Abstract: A variable attenuator is an attenuator which is formed by coupling two transmission lines having an electrical length of ?/4 corresponding to a wavelength ? of an input signal, has one end of one transmission line as an input terminal, has the other end of the one transmission line as a through terminal, has one end of the other transmission line as a coupling terminal and has the other end of the other transmission line as an output terminal, wherein the variable attenuator has a resistor pair having the same impedance at both the through terminal and the coupling terminal, and has a resistor pair having the same impedance at both the input terminal and the output terminal.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: March 22, 2022
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Akio Oya
  • Patent number: 11270967
    Abstract: There is provided a method for manufacturing a semiconductor device comprising: forming a first organic insulating layer on a semiconductor region; forming a bump base film including an edge portion contacting with the first organic insulating layer; performing heat treatment of the bump base film; and forming a second organic insulating layer so as to cover the edge portion of the bump base film and the first organic insulating layer around the bump base film while contacting with the first organic insulating layer, the second organic insulating layer being provided with a first opening that exposes a surface of the bump base film.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: March 8, 2022
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Keita Matsuda
  • Patent number: 11264781
    Abstract: A manufacturing method for an optical semiconductor device includes: forming a first semiconductor layer; forming a first mask pattern on the first semiconductor layer in a first area where an electro absorption type modulator is formed; forming an unevenness along the first direction on the first semiconductor layer; forming a second semiconductor layer on the unevenness; and forming an optical waveguide layer on the second semiconductor layer. The first mask pattern includes a first pattern in the first area and a second pattern in a second area where a DFB laser is formed, the first pattern including a first opening pattern and a first cover pattern, and the second pattern including a second opening pattern and a second cover pattern, and a ratio of the first opening pattern to the first cover pattern is different from that of the second opening pattern to the second cover pattern.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: March 1, 2022
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Kazuhiro Yamaji, Takayuki Watanabe
  • Patent number: 11264341
    Abstract: Provided is a microwave integrated circuit including: a semiconductor substrate; a plurality of amplification units that are formed in the semiconductor substrate; a wiring that is formed in one layer wiring excluding an uppermost layer wiring and a lowermost layer wiring among a plurality of layer wirings formed on the semiconductor substrate and is used for supplying power to the plurality of amplification units; and a plurality of vias that connect a plurality of conductive regions formed in the layer wiring with the wiring interposed therebetween and other conductive regions formed in a region interposing the wiring in the two layer wirings immediately above and immediately below the layer wiring, in which each of the plurality of vias forms a via structure connected to the conductive regions of the lowermost layer wiring by a plurality of other vias.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: March 1, 2022
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Kenshi Naito
  • Publication number: 20220005751
    Abstract: A semiconductor device package is disclosed. The package according to one example includes a base having a main surface made of a metal, a dielectric side wall having a bottom surface facing the main surface, a joining material containing silver (Ag) and joining the main surface of the base and the bottom surface of the side wall to each other, a lead made of a metal joined to an upper surface of the side wall on a side opposite to the bottom surface, and a conductive layer not containing silver (Ag). The conductive layer is provided between the bottom surface and the upper surface of the side wall at a position overlapping the lead when viewed from a normal direction of the main surface. The conductive layer is electrically connected to the joining material, extends along the bottom surface, and is exposed from a lateral surface of the side wall.
    Type: Application
    Filed: February 13, 2020
    Publication date: January 6, 2022
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Shingo INOUE, Kaname EBIHARA
  • Publication number: 20210405307
    Abstract: An optical module includes a first optical splitting element to split a signal beam into a first polarization component and a second polarization component, a first element having a first introduction port, a second element having a second introduction port, a first condensing part disposed between the first optical splitting element and the first introduction port and configured to condense the first polarization component toward the first introduction port, and a second condensing part disposed between the first optical splitting element and the second introduction port and configured to condense the second polarization component toward the second introduction port. An average refractive index of the second condensing part in an optical axis direction is larger than an average refractive index of the first condensing part in an optical axis direction.
    Type: Application
    Filed: July 1, 2020
    Publication date: December 30, 2021
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Satoru KANEMARU
  • Publication number: 20210351147
    Abstract: A method for manufacturing a semiconductor device includes forming a thermosetting resin film on a first metal layer, forming an opening in the resin film, forming a second metal layer that covers a region from an upper surface of the first metal layer exposed from the opening of the resin film to an upper surface of the resin film, performing heat treatment at a temperature equal to or higher than a temperature at which the resin film is cured after forming the second metal layer, forming a cover film that covers the upper surface of the resin film and a side surface of the second metal layer after performing the heat treatment, and forming a solder on an upper surface of the second metal layer exposed from an opening of the cover film after forming the cover film.
    Type: Application
    Filed: April 22, 2021
    Publication date: November 11, 2021
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Keita MATSUDA
  • Publication number: 20210335992
    Abstract: A capacitor having a MIM structure includes a dielectric formed by laminating a plurality of times on an upper surface of a lower electrode, and an upper electrode on an upper surface of the dielectric. Forming of the dielectric includes forming the first dielectric layer on the upper surface of the lower electrode, cleaning an upper surface of the first dielectric layer by at least one of jet cleaning and dual fluid cleaning, and forming the second dielectric layer on an upper surface of the cleaned first dielectric layer.
    Type: Application
    Filed: July 7, 2021
    Publication date: October 28, 2021
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Yoshihide KOMATSU, Takeshi IGARASHI, HIroyuki OGURI
  • Publication number: 20210327827
    Abstract: A field effect transistor includes: a semiconductor region including a first inactive region, an active region, and a second inactive region arranged side by side in a first direction; a gate electrode, a source electrode, and a drain electrode on the active region; a gate pad on the first inactive region; a gate guard on and in contact with the semiconductor region, the gate guard being apart from the gate pad and located between an edge on the first inactive region side of the semiconductor region and the gate pad; a drain pad on the second inactive region; a drain guard on and in contact with the semiconductor region, the drain guard being apart from the drain pad and located between an edge on the second inactive region side of the semiconductor region and the drain pad; and a metal film electrically connected to the gate guard.
    Type: Application
    Filed: June 30, 2021
    Publication date: October 21, 2021
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Chihoko AKIYAMA
  • Patent number: 11152342
    Abstract: A receiver optical module that receives an optical signal and generating an electrical signal corresponding to the optical signal is disclosed. The module includes a photodiode (PD), a sub-mount, a pre-amplifier, and a stem. The sub-mount, which is made of insulating material, mounts the PD thereon. The pre-amplifier, which receives the photocurrent generated by the PD, mounts the PD through the sub-mount with an adhesive. The pre-amplifier generates an electrical signal corresponding to the photocurrent and has signal pads and other pads. The stem, which mounts the pre-amplifier, provides lead terminals wire-bonded with the signal pads of the pre-amplifier. The signal pads make distances against the sub-mount that are greater than distances from the other pads to the sub-mount.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: October 19, 2021
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Kyohei Maekawa
  • Patent number: 11152457
    Abstract: A method of manufacturing a capacitor having an MIM structure includes forming a dielectric by laminating a plurality of times on an upper surface of a lower electrode, and forming an upper electrode on an upper surface of the dielectric. The forming of the dielectric includes forming a first dielectric layer on the upper surface of the lower electrode, cleaning an upper surface of the first dielectric layer by at least one of jet cleaning and dual fluid cleaning, and forming a second dielectric layer on the cleaned upper surface of the first dielectric layer.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: October 19, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Yoshihide Komatsu, Takeshi Igarashi, Hiroyuki Oguri
  • Publication number: 20210313297
    Abstract: A method for manufacturing an electronic component includes preparing a mounting substrate provided with a first region to mount an electronic component thereon and a second region having conductivity, covering the second region with resin, applying a metal paste on the first region, mounting the electronic component on the first region with the metal paste, and removing the resin covering the second region. The mounting includes heating the mounting substrate to cure the metal paste with the electronic components being placed on the metal paste applied on the first region. The resin peeled from the second region by the heating is removed in the removing.
    Type: Application
    Filed: June 8, 2020
    Publication date: October 7, 2021
    Applicant: Sumitomo Electric Device Innovations, Inc.
    Inventor: Taketo KAWANO
  • Publication number: 20210305169
    Abstract: A method for manufacturing a semiconductor device includes forming an insulating film on a region of a substrate serving as a scribe line, forming a first semiconductor layer in a state where a cavity is provided on the insulating film, forming a second semiconductor layer on the first semiconductor layer, and dividing the substrate, the first semiconductor layer and the second semiconductor layer into a plurality of pieces by pressing the substrate at a position corresponding to the region serving as the scribe line on a surface of the substrate opposite to a surface on which the first semiconductor layer is formed.
    Type: Application
    Filed: March 4, 2021
    Publication date: September 30, 2021
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Tadahiro HACHUDA