Abstract: Systems and methods are presented for forming a gate structure comprising an insulative portion, whereby the insulative portion is utilized to electrically isolate an electrically conductive portion of the gate structure from a conductive element located in the vicinity of the gate structure. The insulative portion is formed by chemically modifying a conductive portion of the gate. Chemical modification is an oxidation process, converting aluminum conductor to aluminum oxide insulator material. Utilizing a chemically modified gate structure enables self aligning contact technique(s) to be utilized with semiconductor devices comprising a replacement metal gate(s). The chemical modification process can be performed prior or after forming a contact opening.

Abstract: A temperature sensor generates a digital output signal representative of the absolute temperature of the sensor. The sensor includes a first circuit configured to generate a complementary to absolute temperature (CTAT) voltage signal and a second circuit configured to generate a proportional to absolute temperature (PTAT) current signal. A comparator receives the CTAT and PTAT signals and generates a comparison signal based on a comparison between the signals. A converter circuit receives the comparison signal and generates a digital output signal based on the comparison signal. The digital output signal is representative of the temperature of the sensor.

Abstract: An embedded epitaxial semiconductor portion having a different composition than matrix of the semiconductor substrate is formed with a lattice mismatch and epitaxial alignment with the matrix of the semiconductor substrate. The temperature of subsequent ion implantation steps is manipulated depending on the amorphizing or non-amorphizing nature of the ion implantation process. For a non-amorphizing ion implantation process, the ion implantation processing step is performed at an elevated temperature, i.e., a temperature greater than nominal room temperature range. For an amorphizing ion implantation process, the ion implantation processing step is performed at nominal room temperature range or a temperature lower than nominal room temperature range. By manipulating the temperature of ion implantation, the loss of strain in a strained semiconductor alloy material is minimized.

Abstract: Systems and methods are presented for controlling formation of a silicide region. A selective etch layer is utilized to control formation of a trench opening, and further can be utilized to open up a trench to facilitate correct exposure of an active Si region to subsequently form a silicide. Issues regarding over-dimension, under-dimension, and misalignment of a trench are addressed. The selective etch material is chosen to facilitate control of the trench formation and also to enable removal of the selective etch layer without affecting any adjacent structures/material. The selective etch layer can be an oxide, for example aluminum oxide, Al2O3. The selective etch layer can be utilized to prevent formation of silicide in a channel beneath a raised source/drain.

Abstract: Described herein are methods and systems for efficiently preparing a wafer layout for processing into a photomask. Portions of layouts containing semiconductor features and designs that are frequently used can be stored in a database. These portions can be post-decomposition, with all treatment and error checking already performed upon them. When a wafer layout is received for processing into a photomask, the processing and decomposition time can be reduced by analyzing the layout, and replacing sections of the layout with the portions from the database that have already been decomposed and processed. As these sections no longer need to be decomposed, error checked, and treated, the processing time is greatly reduced, and photomasks can be made quicker and more efficiently.

Abstract: A hybrid drive and associated methods increase the rate at which data are transferred to a nonvolatile storage medium in the hybrid drive. By using a large nonvolatile solid state memory device as cache memory for a magnetic disk drive, a very large number of write commands can be cached and subsequently reordered and executed in an efficient manner. In addition, strategic selection and reordering of only a portion of the write commands stored in the nonvolatile solid state memory device increases efficiency of the reordering process.

Abstract: A low power maskless inter-well deep trench isolation structure and methods of manufacture such structure are provided. A method includes depositing a plurality of layers over a substrate, and forming a layer over the plurality of layers. The method also includes forming well structures in the substrate, and forming sidewall spacers at opposing sides of the layer. The method further includes forming a self-aligned deep trench in the substrate to below the well structures, by removing the sidewall spacers and portions of the substrate aligned with an opening formed by the removal of the sidewall spacers. The method also includes forming a shallow trench in alignment with the deep trench. The method further includes forming shallow trench isolation structures and deep trench isolation structures by filling the shallow trench and the deep trench with insulator material.

Abstract: Semiconductor devices and methods of making semiconductor devices are provided. Boron diffusion into source/drain regions is restricted by a vertical and lateral confinement area formed on the surfaces of the source/drain regions. In an aspect, a silicon-carbon layer formed on the surface of the channel region suppresses boron diffusion toward a first source/drain region and toward at least a second source/drain region.

Abstract: A metallic liner stack including at least a Group VIIIB element layer and a CuMn alloy layer is deposited within a trench in a dielectric layer. Copper is deposited on the metallic liner stack and planarized to form a conductive interconnect structure, which can be a metal line, a metal via, or a combination thereof. The deposited copper and the metallic liner stack are annealed before or after planarization. The Mn atoms are gettered by the Group VIIIB element layer to form a metallic alloy liner including Mn and at least one of Group VIIIB elements. Mn within the metallic alloy liner combines with oxygen during the anneal to form MnO, which acts as a strong barrier to oxygen diffusion, thereby enhancing the reliability of the conductive interconnect structure.

Abstract: Described herein are semiconductor devices with a threshold voltage (Vt) adjusted through back gate stack engineering to meet performance and power requirements and corresponding back gate stack engineering methods. The semiconductor devices can include a thin SOI region, a thin BOX region and a semiconductor substrate. The threshold voltage can be adjusted in the backside of the semiconductor device through implantation of one or more dopants into the BOX region such that the peak concentration of the one or more dopants is inside the BOX region.

Abstract: Described herein are methods for copper/low-k dielectric material integration. The methods involve depositing and curing a low-k dielectric material and depositing a mask on the low-k dielectric material. A via is patterned in the low-k dielectric material and a trench is patterned in the low-k dielectric material. After the via or trench is patterned, a portion of the low-k material is backfilled with a backfill material. The trench and via are filled with copper, then the mask and the copper filling the via are removed. After a first pre-CLN, the backfill material is removed. This creates a robust copper/porous low-k dielectric material interconnect.

Abstract: Methods and structure are provided for utilizing a dielectric mask layer having a gradated density structure. The density of the dielectric mask layer is greatest at the interface of the dielectric mask layer and an underlying dielectric layer. The density of the dielectric mask layer is lowest at the interface of the dielectric mask layer and an overlaying hard mask. The lower density dielectric mask layer is more susceptible to removal than the higher density dielectric mask layer. The lower density dielectric mask layer is removed during at least one of an RIE etch or a post-RIE etch wet clean. Selective removal of the lower density dielectric mask layer creates a dielectric mask layer having a rounded profile. The dielectric mask layer comprises tetraethyl orthosilicate.

Abstract: Methods and structure are provided to facilitate isolation of respective ground plane regions in an SOTB semiconductor device. In one aspect a shallow STI trench can be combined with Si:C or Si:C/SiGe layers to confine n-type and p-type regions. In a further aspect, Ge can be implanted at the bottom of a shallow STI trench and subsequently oxidized to form SiGe oxide thereby extending the effective isolation provided by the shallow STI trench. In an aspect, a shallow STI trench can be extended to expose an underlying layer of SiGe, wherein the SiGe is subsequently oxidized to extending the effective isolation provide by the shallow STI trench. Such aspects enable a shallow STI trench to be seamlessly filled while having an extended region of isolation.

Abstract: Preamble fields are written on a storage disk in a hard disk drive in a way that reduces track squeeze. Preamble fields for a particular data storage track on the storage disk are written over multiple revolutions of the storage disk to eliminate low-frequency variations of the preamble stitch line from an ideal position of the preamble stitch line.

Abstract: Described herein are methods for forming a semiconductor structure. The methods involve forming a doped semiconductor film, amorphizing the doped semiconductor film through ion implantation; and annealing the doped semiconductor film. The ion implantation and the annealing can increase an activation efficiency of the dopant. The ion implantation and the annealing can also reduce a number of crystalline defects in the doped semiconductor film.

Abstract: Semiconductor devices and methods of making semiconductor devices are provided. According to one embodiment, the field effect transistor can contain a semiconductor substrate containing shallow trench isolations; a p-FET and an n-FET; a silicon germanium layer in a recess in the upper surface of the p-FET; a pair of gate dielectrics including a hafnium compound and a rare earth compound disposed on the silicon germanium layer and the upper surface of the n-FET; and a pair of gate electrodes both including the same material disposed on the pair of gate dielectrics.

Abstract: Methods and structure are provided for creating and utilizing hard masks to facilitate creation of a grating effect to control an anisotropic etching process for the creation of an opening, and subsequent formation of a interconnect structure (e.g., a via) in a multilayered semiconductor device. A first hard mask can be patterned to control etching in a first dimension, and a second hard mask can be patterned to control etching in a second dimension, wherein the second hard mask is patterned orthogonally opposed to the first hard mask. A resist can be patterned by inverting the pattern of a metal line patterning. Interconnects can be formed with critical dimension(s) and also self-aligned.

Abstract: Overlay control methods, semiconductor manufacturing method and a semiconductor manufacturing apparatus are provided for restraining overlay error between lithography processes, of a semiconductor manufacturing process, within a tolerance of a semiconductor device. According to one or more aspects, enhanced overlay control mechanisms are provided to enable previous layers to perform corrections to an extent that does not exceed a correction ability of a next layer. For instance, the next layer can inform the previous layer of a tolerated range that is correctable so that the previous layer can perform corrections without exceeding the tolerate range. Accordingly, a feedback loop is established that extends across two exposure events and is not closed within a single exposure event as with conventional systems.

Abstract: A test structure, a method of employing the test structure, and a method of manufacturing the test structure are provided for measuring a contact resistance between a silicide and a semiconductor. The test structure includes a set of silicide layers separated from one another and upon which electrodes from a set of electrodes are placed. One pair of electrodes is employed to force a constant current through the silicide layers and a diffusion layer of a semiconductor substrate of the test structure. Another pair of electrodes determines a potential drop between the silicide layers and the diffusion layer. Based upon the constant current and the potential drop determined, a contact resistance is extracted.

Abstract: According to certain embodiments, a resist is placed over the surface of a semiconductor structure, wherein the resist covers a portion of the semiconductor structure. Dopants are implanted into the semiconductor structure using an ion implantation beam in regions of the semiconductor structure not covered by the resist. Due to exposure to the ion implantation beam, at least a portion of the resist is converted by exposure to the ion beam to contain an inorganic carbonized material. The semiconductor structure with resist is contacted with a superacid composition containing a superacid species to remove the resist containing inorganic carbonized materials from the semiconductor structure.