Abstract: Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

Abstract: An embedded epitaxial semiconductor portion having a different composition than matrix of the semiconductor substrate is formed with a lattice mismatch and epitaxial alignment with the matrix of the semiconductor substrate. The temperature of subsequent ion implantation steps is manipulated depending on the amorphizing or non-amorphizing nature of the ion implantation process. For a non-amorphizing ion implantation process, the ion implantation processing step is performed at an elevated temperature, i.e., a temperature greater than nominal room temperature range. For an amorphizing ion implantation process, the ion implantation processing step is performed at nominal room temperature range or a temperature lower than nominal room temperature range. By manipulating the temperature of ion implantation, the loss of strain in a strained semiconductor alloy material is minimized.

Abstract: A driver boost signaling circuit provides a pulse boost to the first cycle of an output pulse wave applied to an associated load. The circuit includes a signal generator circuit generating a signal including a series of pulses, a determining circuit determining a high impedance state of a signal load line and a first one or more cycles of the series of pulses applied to the load line following the high impedance condition, and a receiving circuit receiving a control signal. A logic circuit generates first and second logical signals responsive to the control signal and to the determining circuit determining the first one or more cycles and other cycles of the series of pulses.

Abstract: A metallic liner stack including at least a Group VIIIB element layer and a CuMn alloy layer is deposited within a trench in a dielectric layer. Copper is deposited on the metallic liner stack and planarized to form a conductive interconnect structure, which can be a metal line, a metal via, or a combination thereof. The deposited copper and the metallic liner stack are annealed before or after planarization. The Mn atoms are gettered by the Group VIIIB element layer to form a metallic alloy liner including Mn and at least one of Group VIIIB elements. Mn within the metallic alloy liner combines with oxygen during the anneal to form MnO, which acts as a strong barrier to oxygen diffusion, thereby enhancing the reliability of the conductive interconnect structure.

Abstract: Multi-gate metal oxide silicon transistors and methods of making multi-gate metal oxide silicon transistors are provided. The multi-gate metal oxide silicon transistor contains a bulk silicon substrate containing one or more convex portions between shallow trench regions; one or more dielectric portions over the convex portions; one or more silicon fins over the dielectric portions; a shallow trench isolation layer in the shallow trench isolation regions; and a gate electrode. The upper surface of the shallow trench isolation layer can be located below the upper surface of the convex portion, or the upper surface of the shallow trench isolation layer can be located between the lower surface and the upper surface of first dielectric layer. The multi-gate metal oxide silicon transistor can contain second spacers adjacent to side surfaces of the convex portions in a source/drain region.

Abstract: A non-inverting AC/DC input buffer combines the desirable characteristics of an alternating current (AC) input buffer including low delay, high speed, and high input voltage swing range with the desirable characteristics of a direct current (DC) input buffer including stability, reliability, and ‘automatic’ high and low data setup. The AC/DC buffer includes logic to help prevent the DC input buffer from interfering with the AC input buffer until the DC input buffer has completed its operations on a transitioning input. The DC buffer is configured to enable the AC buffer to process low input voltage swings such as, for example, voltage swings less than the difference in power supply voltages.

Abstract: Field effect transistors and methods of making field effect transistors are provided. The field effect transistor can contain a semiconductor substrate containing shallow trench isolations; a silicon germanium layer in a trench at an upper surface of the semiconductor substrate between the shallow trench isolations; a gate feature on the silicon germanium layer; and metal silicides on the upper potions of silicon germanium layer and semiconductor substrate that are not covered by the gate feature. The silicon germanium layer has a bottom surface and a top surface having a (100) plane and side surfaces having two or more planes.

Abstract: A Direct Silicon Bonded substrate can include a first substrate and a second substrate in which the second substrate can be rotated to an azimuthal twist angle of 45 degrees in comparison to the first substrate. Disclosed are a semiconductor device and a method for making a semiconductor device that includes a DSB substrate with an adjusted thickness based upon the threshold voltage (Vt). In other words, a thicker substrate or layer can correspond to a high threshold voltage (HVt) and a thinner substrate or layer can correspond to a low threshold voltage (LVt) in order to improve mobility in LVt devices.

Abstract: A semiconductor device includes: a substrate and an n-channel MIS transistor. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, wherein a first source/drain region is formed in the p-type semiconductor region and separated from each other. The n-channel MIS transistor includes a first gate insulating film on the p-type semiconductor region between the first source/drain regions. The n-channel MIS transistor further includes a first gate electrode having a stack structure formed with a gate dielectric, a first metal layer and a first compound layer, the first metal layer having a thickness less than 2 nm and having a work function of 4.3 eV or smaller, the first metal layer being formed on the metallic layer having a work function larger than 4.4 eV and the first compound layer containing Al and a second metal that is different from the first metal.

Abstract: Methods of making interconnect structures are provided. In one aspect of the innovation, when forming a trench or via in a dielectric layer, the sidewall surface of another via and/or trench is covered with a metal oxide layer. The metal oxide layer can prevent and/or mitigate surface erosion of the sidewall surface. As a result, the methods can improve the controllability of critical dimensions of the via and trench.

Abstract: Back end of line interconnect structures and methods of making a back end of line interconnect structure are provided. The back end of line interconnect structure contains a first interconnect layer containing a first conductive feature and a first dielectric layer; a first cap layer over the first interconnect layer, and a second interconnect layer over the first cap layer. The second interconnect layer contains a second conductive feature, a second dielectric layer, and two or more barrier layers therebetween. The two or more barrier layers contain a first barrier layer over the second dielectric layer and a MnOx-containing barrier layer over the first barrier layer. Containing the MnOx-containing barrier layer, the back end of line interconnect structure can prevent and/or mitigate diffusion of conductive material of the second conductive feature therethrough.

Abstract: A SRAM bit cell and an associated method of producing the SRAM bit cell with improved performance and stability is provided. In one configuration, channel mobility of the transistors within the SRAM bit cell may be adjusted to provide improved stability. In order to adjust the channel mobility, a stress memorization technique may be used, a wide spacer may be used, germanium may be implanted on tensile stress silicon nitride, a compressive liner may be used or silicon germanium may be embedded in one or more of the devices in the cell. In another configuration, the gate capacitance of each device within the SRAM bit cell may be adjusted to achieve high SRAM yield. For instance, a thick gate oxide may be used, phosphorous pre-doping may be used or fluorine pre-doping may be used in one or more of the devices within the cell.

Abstract: Gate electrode structures having a thin layer of ReO3 formed with high effective work function and high heat resistance are disclosed. The thin layer of ReO3 is formed by providing a semiconductor structure having an oxygen-containing metal alloy layer and a rhenium layer. A heat annealing step diffuses Re from the rhenium layer through the high-oxygen containing metal alloy layer to form a thin layer of ReO3.

Abstract: Disclosed are methods of making an integrated circuit with multiple thickness and/or multiple composition high-K gate dielectric layers and integrated circuits containing multiple thickness and/or multiple composition high-K gate dielectrics. The methods involve forming a layer of high-K atoms over a conventional gate dielectric and heating the layer of high-K atoms to form a high-K gate dielectric layer. Methods of suppressing gate leakage current while mitigating mobility degradation are also described.

Abstract: Static random access memory cells and methods of making static random access memory cells are provided. The static random access memory cells contain two non-planar pass-gate transistors, two non-planar pull-up transistors, two non-planar pull-down transistors. A portion of a fin of the non-planar pull-up transistor is electrically connected to a portion of a fin of the non-planar pull-down transistor by an assist-bar. The methods involve forming an assist-fin between fins of a non-planar pull-up transistor and a non-planar pull-down transistor and between gate electrodes, and widening a width of the assist-fin to form the assist-bar so that a portion of the fin of non-planar pull-up transistor is electrically connected to a portion of the fin of non-planar pull-down transistor via the assist-bar.

Abstract: Techniques for arranging ball grid arrays for producing low thermal resistance packages. One embodiment is for a ball grid array package that comprises a substrate, the substrate having a top surface and a bottom surface. A plurality of thermal balls are coupled to the bottom surface of the substrate, and at least one vias is positioned between every pair of the plurality of thermal balls. Other embodiments contemplate a ball grid array comprising thermal balls with a via located between every four thermal balls, wherein at least one vias is substituted for a thermal ball in the ball grid array.

Abstract: An interconnect method in a semiconductor device may include a step of examining various regions of an inter layer dielectric to identify regions having high densities or concentrations of trench features. A cap insulator layer may be added to the dielectric to assist in outgassing of absorbed impurities from the dielectric, but may be removed from the high density areas to allow the lower density areas to increase outgassing. The lower density areas may then compensate for increased outgassing on the high density areas due to the trench features, and may result in an overall device with a more stable dielectric constant across the device.

Abstract: The invention relates to an apparatus comprising a pipelined converter, such as a pipelined ADC. The pipelined converter has a first set of stages and a second set of stages. A clocking circuit is configured to generate a plurality of clocking signals for the pipelined converter. The plurality of clocking signals comprise a first clocking signal at a first voltage level that is provided to the first set of stages and a second clocking signal at a second voltage level that is provided to the second set of stages.

Abstract: A method for manufacturing a semiconductor device may comprise forming a conductive layer on a substrate, removing at least one portion of the conductive layer to form a plurality of separate conductive lines, forming a first stress-inducing layer of a first stress type on the conductive lines and the substrate, and removing a portion of the first stress-inducing layer such that a remaining portion of the first stress-inducing layer is disposed on a first subset of the conductive lines but not a second subset of the conductive lines and has a boundary disposed between two of the conductive lines. This method, along with other methods and various semiconductor devices, are described.

Abstract: Methods and systems for embodiments of a 9T memory cell, memory devices which utilize such 9T memory cells and the creation of embodiments of such memory devices are disclosed. More specifically, an embodiment of a 9T memory cell may comprise a 6T memory cell portion and a 3T read port. Additionally, in one embodiment, a memory which utilizes 9T memory cells may be made by from a grid comprising columns and rows of transistors formed according to a layout for 6T memory cells.