Patents Assigned to Toshiba America Electronic Components, Inc.
  • Method for controlling operation of microprocessor which performs duty cycle correction process
    Patent number: 7716516
    Abstract: A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: May 11, 2010
    Assignees: Sony Computer Entertainment Inc., International Business Machines Corporation, Toshiba America Electronic Components, Inc.
    Inventors: Yosuke Muraki, Tetsuji Tamura, Iwao Takiguchi, Makoto Aikawa, Eskinder Hailu, Byron Lee Krauter, Stephen Douglas Weitzel, Jieming Qi, Kazuhiko Miki, David William Boerstler, Gilles Gervais, Kirk David Peterson, Robert Walter Berry, Jr., Sang Hoo Dhong
  • Time base corrector
    Patent number: 7702056
    Abstract: A system and method for synchronizing a system clock in accordance with a program clock reference of a content data stream includes application of incremental delays to a local clock signal having a higher frequency than that specified by the program clock reference. The delay is made over a period defined by phase comparison between a system clock signal and a minimum delay value. Delay values are incremented proportionally to a number of clock cycles over the period. The subject system allows for display of jitter free audio or video decoded from the content data stream, and is realized in circuitry that is readily implement on an integrated circuit.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: April 20, 2010
    Assignee: Toshiba America Electronic Components, Inc.
    Inventor: Masao Kaizuka
  • Step-embedded SiGe structure for PFET mobility enhancement
    Patent number: 7696537
    Abstract: A device, and method for manufacturing the same, including a PFET having an embedded SiGe layer where a shallow portion of the SiGe layer is closer to the PFET channel and a deep portion of the SiGe layer is further from the PFET channel. Thus, the SiGe layer has a boundary on the side facing toward the channel that is tapered. Such a configuration may allow the PFET channel to be compressively stressed by a large amount without necessarily substantially degrading extension junction characteristics. The tapered SiGe boundary may be configured as a plurality of discrete steps. For example, two, three, or more discrete steps may be formed.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: April 13, 2010
    Assignee: Toshiba America Electronic Components, Inc.
    Inventor: Yusuke Kohyama
  • Reversely tapered contact structure compatible with dual stress liner process
    Patent number: 7652335
    Abstract: A semiconductor device having a silicon layer, a transistor having an electrical connection region in the silicon layer; and a conductive plug formed on and in electrical contact with the electrical connection region, the plug having side walls that taper inward away from the silicon layer.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: January 26, 2010
    Assignee: Toshiba America Electronics Components, Inc.
    Inventor: Katsura Miyashita
  • Dual Stress Liner Device and Method
    Publication number: 20090289375
    Abstract: A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device, and the uppermost overlapping layer may be polished down in a process that uses the bottom overlapping layer as a stopper. An insulating film may be deposited on the stress liner layers before the polishing, and another insulating film may be deposited above the first insulating film after the polishing. Contacts may be formed such that the contacts need only penetrate one stress liner layer to reach a transistor well or gate structure.
    Type: Application
    Filed: August 4, 2009
    Publication date: November 26, 2009
    Applicant: Toshiba America Electronic Components, Inc.
    Inventor: Gaku SUDO
  • SOI bottom pre-doping merged e-SiGe for poly height reduction
    Patent number: 7605042
    Abstract: Semiconductor device structures, and methods for making such structures, are described that provide for fully-doped transistor source/drain regions while reducing or even avoiding boron penetration into the transistor channel, thereby improving the performance of the transistor. In addition, such a transistor may benefit from an SiGe layer that applies compressive stress to the transistor channel, thereby further improving the performance of the transistor.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: October 20, 2009
    Assignee: Toshiba America Electronic Components, Inc.
    Inventor: Yusuke Kohyama
  • Stress relaxation for top of transistor gate
    Patent number: 7592653
    Abstract: An improved way to apply tensile or compressive stress to one or more transistors on a semiconductor device is described. A portion of the tensile or compressive stress liner may be removed or modified such that a reduced amount of stress, or even no stress, is applied above the transistor gate. This may cause edges of the stress liner to be adjacent to and on either side of the channel, thus, increasing the stress effect. To produce this stress liner structure, the stress liner may be applied and then a portion of the stress liner is modified to reduce the stress in that portion, such as through ion implantation. The stress liner portion may be modified to have a reduced stress by, for example, implanting certain ions such as germanium or xenon ions therein.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: September 22, 2009
    Assignee: Toshiba America Electronic Components, Inc.
    Inventor: Gaku Sudo
  • Generating Stress in a Field Effect Transistor
    Publication number: 20090224263
    Abstract: A structure for generating stress in a field effect transistor is described. Combinations of materials are described that when juxtaposed provide one of tensile or compressive stress to a channel region. In one or more aspects, tensile stress is provided to a channel region by materials having similar but different lattice constants.
    Type: Application
    Filed: March 6, 2008
    Publication date: September 10, 2009
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Katsura Miyashita
  • MASKLESS SELECTIVE BORON-DOPED EPITAXIAL GROWTH
    Publication number: 20090224368
    Abstract: A semiconductor device, comprising a silicon layer, an n-type field-effect transistor (NFET) disposed in and on a silicon layer, and a p-type field-effect transistor (PFET) disposed in and on the silicon layer, wherein the PFET includes a boron-doped silicon-germanium layer disposed on the silicon layer. Also, a method for manufacturing a semiconductor device, comprising forming a first conductive layer over a p-well of a silicon layer, forming a second conductive layer over an n-well of the silicon layer, implanting fluorine ions into both the p-well and the n-well, exposing both the p-well and the n-well to ammonium hydroxide and peroxide, and epitaxially growing a boron-doped silicon-germanium layer on the silicon layer.
    Type: Application
    Filed: March 3, 2009
    Publication date: September 10, 2009
    Applicant: Toshiba America electronic Components, Inc.
    Inventor: Gaku Sudo
  • Dual stress liner device and method
    Patent number: 7585720
    Abstract: A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device, and the uppermost overlapping layer may be polished down in a process that uses the bottom overlapping layer as a stopper. An insulating film may be deposited on the stress liner layers before the polishing, and another insulating film may be deposited above the first insulating film after the polishing. Contacts may be formed such that the contacts need only penetrate one stress liner layer to reach a transistor well or gate structure.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: September 8, 2009
    Assignee: Toshiba America Electronic Components, Inc.
    Inventor: Gaku Sudo
  • Contact Configuration and Method in Dual-Stress Liner Semiconductor Device
    Publication number: 20090206414
    Abstract: A method for manufacturing a semiconductor device may comprise forming a conductive layer on a substrate, removing at least one portion of the conductive layer to form a plurality of separate conductive lines, forming a first stress-inducing layer of a first stress type on the conductive lines and the substrate, and removing a portion of the first stress-inducing layer such that a remaining portion of the first stress-inducing layer is disposed on a first subset of the conductive lines but not a second subset of the conductive lines and has a boundary disposed between two of the conductive lines. This method, along with other methods and various semiconductor devices, are described.
    Type: Application
    Filed: February 14, 2008
    Publication date: August 20, 2009
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Gaku Sudo
  • Method and System for Semiconductor Memory
    Publication number: 20090201719
    Abstract: Methods and systems for embodiments of a 9T memory cell, memory devices which utilize such 9T memory cells and the creation of embodiments of such memory devices are disclosed. More specifically, an embodiment of a 9T memory cell may comprise a 6T memory cell portion and a 3T read port. Additionally, in one embodiment, a memory which utilizes 9T memory cells may be made by from a grid comprising columns and rows of transistors formed according to a layout for 6T memory cells.
    Type: Application
    Filed: February 12, 2008
    Publication date: August 13, 2009
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Takaaki Nakazato
  • Semiconductor device using buried oxide layer as optical wave guides
    Patent number: 7574090
    Abstract: A semiconductor optical wave guide device is described in which a buried oxide layer (BOX) is capable of guiding light. Optical signals may be transmitted from one part of the semiconductor device to another, or with a point external to the semiconductor device, via the wave guide. In one example, an optical wave guide is provided including a core insulating layer encompassed by a clad insulating layer. The semiconductor device may contain an etched hole for guiding light to and from the core insulating layer from a transmitter or to a receiver.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: August 11, 2009
    Assignee: Toshiba America Electronic Components, Inc.
    Inventor: Yoshiaki Shimooka
  • Oven for Semiconductor Wafer
    Publication number: 20090196588
    Abstract: An oven is described that can more evenly heat the semiconductor wafer, even though the wafer may warp during heating. The oven may provide relatively uniform heating even though the type and location of warping may be unpredictable for any given wafer. The oven may have a heating surface divided into a plurality of heating zones that may each independently provide a given amount of heat to the wafer. The amount of heat provided by each zone may be determined using signals from sensors that sense the warping of the wafer.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 6, 2009
    Applicant: Toshiba America Electronic Components, Inc.
    Inventor: Seiji Nakagawa
  • Semiconductor device with close stress liner film and method of manufacturing the same
    Patent number: 7569888
    Abstract: Aspects of the present disclosure are generally directed to FETs with stress liners that are closer than typical stressed FETs, as well as methods for manufacturing the same. FETE channel sidewall spacers may be removed, or substantially reduced in width, prior to forming the stress liners. This may be performed without destroying the underlying thin oxide layer. The sidewall spacers may be removed substantially reduced either prior to or after silicide formation. Where the sidewall spacers are removed prior to silicide formation, a relatively thin oxide layer on opposing sides of the channel may be used as a mask when forming the silicide. In addition, devices having both an NFET with a closer-than-typical tensile liner and a PFET with a closer-than-typical compressive liner, as well as methods for manufacturing the same, are disclosed.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: August 4, 2009
    Assignee: Toshiba America Electronic Components, Inc.
    Inventor: Gaku Sudo
  • STRUCTURES OF SRAM BIT CELLS
    Publication number: 20090189227
    Abstract: A SRAM bit cell and an associated method of producing the SRAM bit cell with improved performance and stability is provided. In one configuration, channel mobility of the transistors within the SRAM bit cell may be adjusted to provide improved stability. In order to adjust the channel mobility, a stress memorization technique may be used, a wide spacer may be used, germanium may be implanted on tensile stress silicon nitride, a compressive liner may be used or silicon germanium may be embedded in one or more of the devices in the cell. In another configuration, the gate capacitance of each device within the SRAM bit cell may be adjusted to achieve high SRAM yield. For instance, a thick gate oxide may be used, phosphorous pre-doping may be used or fluorine pre-doping may be used in one or more of the devices within the cell.
    Type: Application
    Filed: January 25, 2008
    Publication date: July 30, 2009
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Katsura Miyashita
  • METHOD AND SYSTEM FOR LEVELING TOPOGRAPHY OF SEMICONDUCTOR CHIP SURFACE
    Publication number: 20090190108
    Abstract: A system and method of leveling the topography of a semiconductor wafer surface is presented. The system may induce low-order lens aberration to control the focal plane dynamically. The system may include a leveling sensor which measures the changes in topography on the surface, as well as an analyzer to determine the aberration to be induced. In addition, the system may include a controller that dynamically adjusts at least one lens to induce such aberration. In another arrangement, the system may control the focal plane by dividing the exposure slit into smaller slits. In this arrangement, the analyzer may be used to determine the appropriate number of divisions to make to produce a focal plane that closely matches the surface of the wafer. In addition, the controller may adjust the stage height and tilt for each division to produce such a focal plane.
    Type: Application
    Filed: January 30, 2008
    Publication date: July 30, 2009
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventors: Tatsuhiko Ema, Kenji Konomi
  • STRUCTURES OF SRAM BIT CELLS
    Publication number: 20090189198
    Abstract: An SRAM bit cell structure that can be produced in small sizes while maintaining performance is presented. In one configuration, an SRAM bit cell includes driver field effect transistors that are p-type field effect transistors, load field effect transistors that are n-type field effect transistors and transfer gates that are p-type field effect transistors. Each field effect transistor may be arranged on a substrate that will enhance performance. In one arrangement, the p-type field effect transistors may be arranged on a silicon (110) substrate to enhance hole mobility while the n-type field effect transistors may be arranged on a silicon on insulator (100) substrate to enhance electron mobility. In another arrangement, the load n-type field effect transistor may be arranged on the same silicon (110) substrate as the other field effect transistors in the cell.
    Type: Application
    Filed: January 25, 2008
    Publication date: July 30, 2009
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Katsura Miyashita
  • COATING PROCESS AND EQUIPMENT FOR REDUCED RESIST CONSUMPTION
    Publication number: 20090191720
    Abstract: A coating system and method of coating semiconductor wafers is disclosed that is able to maintain a wet condition on the outer portion of the semiconductor wafer to provide ease of spreading for a photo-resist or anti-reflective coating (ARC) that is being dispensed. The system can include a plurality of nozzles on a movable arm. A first nozzle dispenses a pre-wet solvent onto the semiconductor wafer. A second nozzle then dispenses the photo-resist or ARC coating onto the semiconductor wafer. A third nozzle dispenses additional pre-wet solvent onto the outer edge of the semiconductor wafer as the photo-resist or ARC coating is being dispensed. The nozzles dispense solutions onto the semiconductor wafer as it rotates. The system produces semiconductor wafers with few coating defects and uses less photo-resist or ARC coating.
    Type: Application
    Filed: January 25, 2008
    Publication date: July 30, 2009
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Seiji Nakagawa
  • Trench Sidewall Protection by a Carbon-Rich Layer in a Semiconductor Device
    Publication number: 20090179300
    Abstract: When forming a trench in a porous low-K dielectric (such as an ILD) of a semiconductor device, a carbon-rich layer is formed in the sidewalls of the trench during trench etching. This carbon-rich layer may protect the trench from being excessively etched, which would otherwise form an undesirable hardmask undercut. The carbon-rich layer may be formed simultaneously with and during the etching process, by increasing the amount of carbon available to be absorbed by the ILD during the trench etching process. The existence of the extra available carbon may slow the etching of the carbon-enriched regions of the dielectric.
    Type: Application
    Filed: January 14, 2008
    Publication date: July 16, 2009
    Applicant: Toshiba America Electronic Components, Inc.
    Inventor: Shinya Arai