Abstract: An information processing device, an information processing method, and a program capable of creating a screen more efficiently are provided. An information processing device according to an embodiment includes a display control unit, a reception unit, and a storage control unit. The display control unit displays a display screen for arranging a plurality of components each of which has a predetermined function. The reception unit receives settings of the components designated using the display screen. The storage control unit stores, in a storage device, setting information indicating the settings received. The display control unit displays the display screen on which the components are set in accordance with the setting information.

Abstract: According to one embodiment, a data collection system includes a receiving module configured to receive semi-structured data including first data of a first level and a plurality of second data of a second level, the first data including a plurality of the second data, wherein a plurality of second identification information are respectively set for a plurality of the second data, a database, an information storage module configured to store storage position information indicating storage positions of a plurality of the second identification information in the database, and a registration module configured to write a plurality of the second data to the database based on the storage position information.

Abstract: In one embodiment, an image processing system includes a memory and processing circuitry. The memory is configured to store a predetermined program. The processing circuitry is configured, by executing the predetermined program, to perform processing on an input image by exploiting a neural network having an input layer, an output layer, and an intermediate layer provided between the input layer and the output layer, the input image being inputted to the input layer, and adjust an internal parameter based on data related to the input image, while performing the processing on the input image after training of the neural network, the internal parameter being at least one internal parameter of at least one node included in the intermediate layer, and the input parameter having been calculated by the training of the neural network.

Abstract: A 0-1 combinatorial-optimization-problem is solved under constraint-conditions expressed using inequality expressions. A solution-finding device includes an updating-unit and an output-unit. For each of plural elements associated with first- and second-variables, the updating-unit sequentially updates, for each unit-time between initial-timing and end-timing, the first-variable and the second-variable alternatively. The output-unit outputs the solution of the 0-1 combinatorial-optimization-problem based on the first-variable of each of the plural elements at the end-timing.

Abstract: A secondary battery according to an embodiment includes a container having a pouring hole through which an electrolyte is poured, and housing the electrolyte, poured through the pouring hole, together with an electrode body; and a sealing lid which is fixed to the container and is closing the pouring hole. The sealing lid has a welding mark existing in a ring shape with a depth through the sealing lid to a lid body of the container, and an inner circumferential side molten mark existing in a ring shape overlapping with the welding mark, on the inner circumferential side of the welding mark in the sealing lid, with a depth corresponding to the thickness of the sealing lid.

Abstract: A high electron mobility transistor (HEMT) device with a highly resistive layer co-doped with carbon (C) and a donor-type impurity and a method for making the HEMT device is disclosed. In one embodiment, the HEMT device includes a substrate, the highly resistive layer co-doped with C and the donor-type impurity formed above the substrate, a channel layer formed above the highly resistive layer, and a barrier layer formed above the channel layer. In one embodiment, the highly resistive layer comprises gallium nitride (GaN). In one embodiment, the donor-type impurity is silicon (Si). In another embodiment, the donor-type impurity is oxygen (O).

Abstract: An entropy source extracts noise associated with the sampling of an RC circuit. The decay time of the RC circuit and other parameters are selected so that a buffer used to sample the voltage remains in an indeterminate voltage region over multiple clock cycles to generate random transitions. The entropy source may be implemented to be compliant with government standards for entropy sources utilized to generate random numbers.

Abstract: A solid state drive (SSD) storage system includes a memory controller, host interface, memory channels and solid state memories as storage elements. The completion status of sub-commands of individual read commands is monitored and used to determine an optimal selection for returning data for individual read commands. The completion of a read command may be dependent on the completion of multiple individual memory accesses at various times. The queueing of multiple read commands which may proceed in parallel or out of order causes interleaving of multiple memory accesses from different commands to individual memories. A system and method is disclosed which enables the selection, firstly of completed read commands, independent of the order they were queued and, secondly, of partially completed read commands which are most likely to complete with the least interruption or delay, for data transfer, which in turn improves the efficiency of the data transfer interface.

Abstract: A link layer of a serial protocol is modified to perform early primitive detection. An early primitive detector unit compares an undecoded bit sequence to that corresponding to a particular primitive. A primitive notification is generated in response to identifying a match. Latency is reduced compared with performing link layer decoding and then identifying primitives.

Abstract: A high electron mobility transistor (HEMT) device with enhanced conductivity in the transistor's non-gated access regions and a method for making the HEMT device is disclosed. In one embodiment, the HEMT device includes a heterojunction comprising a barrier layer formed on a channel layer. One or more intervening layers comprising a material suitable for increasing a fixed charge at the heterojunction is formed on a substantially planar surface of the barrier layer opposite the channel layer in the non-gated access region.

Abstract: Solid-state mass storage devices and methods of operation thereof include a solid-state mass storage device that may have a capacitor-based power supply module configured for providing power to the mass storage device. In one embodiment, the mass storage device has a first mode of operation wherein a primary power supply provided by a host system provides power to the mass storage device sufficient for its operation and provides power to the capacitor-based power supply module to recharge the module, and a second mode of operation wherein power is provided to the mass storage device from both the primary power supply and the capacitor-based power supply module. The mass storage device may be capable of providing power from the capacitor-based power supply module to the mass storage device after a voltage level of the capacitor-based power supply module falls below an under voltage lock out level.

Abstract: A high voltage semiconductor structure with a field plate comprising a depletable material that increases the breakdown voltage of the semiconductor structure. A depletion region forms within the depletable field plate which redistributes the electric field and preventing electric charges from concentrating at the corners of the field plate. The thickness, doping concentration, doping uniformity, and geometric shape of the field plates may be adjusted to optimize the effect of the charge redistribution.

Abstract: Mass storage devices and methods of operating thereof adapted for use with a host and for storing data thereof includes at least one non-volatile memory for storing the data, at least one volatile memory, a memory controller configured for reading and writing the data and metadata to and from the non-volatile memory and the volatile memory, and an auxiliary power supply, wherein the memory controller locates the data on the non-volatile memory with the metadata. When processing a write command that requires all data to be written to the non-volatile memory before confirmation is returned to the host computer system that the write command has succeeded, the mass storage device is configured to write the data to the non-volatile memory, write the metadata to the volatile memory, and once the both data and metadata are written, return a completion status of the write command to the host computer system.

Abstract: A method of making an aluminum nitride (AlN) buffer layer over a silicon wafer for a light emitting diode (LED) includes preflowing a first amount of ammonia that is sufficient to deposit nitrogen atoms on the surface of a silicon wafer without forming SiNx, before flowing trimethylaluminum and then a subsequent amount of ammonia through the chamber.

Abstract: The operation of a pool of solid state drives is orchestrated to manage garbage collection and wear leveling. Each individual solid state drive is operated in either an Active Mode in which I/O commands are processed or in a Maintenance Mode in which garbage collection is performed and no I/O commands are processed. The selection of solid state drives in the Active Mode is further selected to achieve wear leveling over the pool of solid state drives. A virtualization layer provides dynamic mapping of virtual volume addresses to physical solid state drives.

Abstract: A method for forming a high electron mobility transistor (HEMT) device with a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN), and an HEMT device formed by the method is disclosed. In one embodiment, the method includes forming a channel layer stack on a substrate, the channel layer stack having a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN). The method further includes forming a barrier layer on the channel layer stack. In one embodiment, the channel layer stack is formed by growing each of the one or more undoped gallium nitride (GaN) layers in growth conditions that suppress the incorporation of carbon in gallium nitride, and growing each of the one or more carbon doped gallium nitride (c-GaN) layers in growth conditions that promote the incorporation of carbon in gallium nitride.

Abstract: Methods of manufacturing circuit boards and circuit boards formed thereby to have a surface that is configured to receive circuitry and a notch of a selectable configuration in a lateral edge along the surface of the circuit board boards, and where the selectable configuration is configured to convey identifying information relating to the circuit boards. Such a circuit board can be produced from a panel containing one or more circuit boards, wherein at least one circuit board has a border adjoined and defined by a partition feature that is configured to enable the circuit board to be physically separated from other portions of the panel. Notches having the same of varying selectable configurations may be formed on the at least one circuit board during the manufacturing of the circuit board.

Abstract: A solid state drive has a power failure savings mode that permits a reduction in holdup time for a temporary backup power supply. The solid state drive stores data in a multi-level cell (MLC) mode. In a power fail saving mode system metadata is written in a pseudo Single Level Cell (pSLC) mode. In the normal operating mode page writes are performed in complete blocks. In the power fail save saving mode data from a write buffer is written and additional dummy pages written to reduce the total number of pages that must be written to below a complete block size with the dummy pages providing protection from data corruption.

Abstract: The present disclosure presents a novel structure for a dielectric material for use with Group III-V material systems and a method of fabricating such a structure. More specifically, the present disclosure describes a novel dielectric layer that is formed on the top surface of a III-V material where the dielectric layer comprises a first region in contact with the top surface of the III-V material crystalline and a second region adjacent to the first region and at the upper side of the dielectric layer. The dielectric layer has material properties different from traditional dielectric layers as it is composed of both crystalline and amorphous structures. The crystalline structure is at the interface with the III-V material (such as AlGaN or GaN) but gradually transitions into an amorphous structure, both within the same layer and both comprising the same material.

Abstract: A system and method thereof to regulate a current to a capacitive load from a power supply connected to the capacitive load. The system includes a first switch between the power supply and the capacitive load, a super-capacitor configured for charging by the power supply and powering the capacitive load, a current limiting circuit between the super-capacitor and the power supply, a second switch between the super-capacitor and the capacitive load, and a power control circuit configured to control opening and closing of the first switch and the second switch independently, sense a voltage of the power supply, and sense a voltage of the super-capacitor.