Abstract: A semiconductor device includes a capacitor. The capacitor includes a first electrode and a second electrode disposed in a first metal layer. The first electrode has a first end and a second end, and the first electrode has a spiral pattern extending outwards from the first end to the second end. The first electrode and the second electrode have a substantially equal spacing therebetween.

Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.

Abstract: A memory device includes a local input/output circuit and a main input/output circuit. The local input/output circuit is configured to generate a first local write signal based on a first global write signal and a second global write signal, and configured to transmit the first local write signal to a plurality of first bit lines. The main input/output circuit include a first latch and logic elements. The first latch is configured to generate a first bit write mask signal based on a clock signal. The logic elements are configured to generate the first global write signal and the second global write signal based on the clock signal and the first bit write mask signal.

Abstract: An integrated circuit includes first to second transistors and a resistive device. The first transistor is coupled between a pad and a first voltage terminal that provides a first supply voltage. The second transistor is coupled in parallel with the first transistor. A breakdown voltage of the first transistor is different from a trigger voltage of the second transistor. The resistive device is coupled between the pad and a second voltage terminal that provides a second supply voltage higher than the first supply voltage, and operates with the second supply voltage in an electrostatic discharge(ESD) event when the first and second transistors discharge a ESD current between the pad and the first voltage terminal.

Abstract: A method is provided and includes the operation below: discharging electrostatic charges from a pad to a first voltage terminal through a first active region coupled to the pad and a second active region coupled between the first active region and the first voltage terminal, in which the first active region and the second active region are the same conductivity type and have different widths from each other, and the first active region and the second active region are included in a first transistor having a first breakdown voltage; and discharging the electrostatic charges through an ESD primary circuit having a first terminal coupled with the first active region and a second terminal coupled with the first voltage terminal. The ESD primary circuit has a trigger voltage lower than the first breakdown voltage.

Abstract: A method includes forming a body region of a first conductivity type and a doped region of a second conductivity type in a semiconductor substrate; forming a gate structure the substrate, and first gate spacers respectively on first and second sides of the gate structure; depositing a second spacer layer and a third spacer layer over the gate structure; patterning the third spacer layer into third gate spacers respectively on the first and second sides of the gate structure; removing a first one of the third gate spacers from the first side of the gate structure, while leaving a second one of the third gate spacers on the second side of the gate structure; and patterning the second spacer layer into a second gate spacer by using the second one of the third gate spacers as an etching mask.

Abstract: A semiconductor device includes a substrate, an active region, an isolation structure, a first metal line, gate structure, source/drain region, a source/drain contact, and a second metal line. The active region protrudes from a top surface of the substrate. The isolation structure is over the substrate and laterally surrounds the active region. The first metal line is in the isolation structure. The gate structure is over the active region. The source/drain region is in the active region. The source/drain contact is over the active region and is electrically connected to the source/drain region. The second metal line is over the gate structure and the source/drain contact, in which the second metal line vertically overlaps the first metal line.

Abstract: A memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The first N-type transistor is coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The first inverter is coupled to the NAND logic gate, and configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

Abstract: A semiconductor device includes a substrate, a gate structure, a drift region, a source region, a drain region, and a doped region. The gate structure is above the substrate. The drift region is in the substrate and under the gate structure. The source region and the drain region are on opposite sides of the gate structure. The drain region is in the drift region, and the source region is outside the drift region. The doped region is in the drift region and between the drain region and the gate structure. The doped region is spaced apart from a bottom surface of the drain region.

Abstract: A memory device includes a first isolation cell, a first memory array of a first memory segment, a second memory array of a second memory segment, a first decoder cell of the first memory segment and a second decoder cell of the second memory segment. The first isolation cell extends in a first direction. The first memory array of the first memory segment abuts a first boundary of the first isolation cell in a second direction different from the first direction. The second memory array of the second memory segment abuts a second boundary, opposite to the first boundary, of the first isolation cell in the second direction. The first decoder cell of the first memory segment and the second decoder cell of the second memory segment are arranged on opposite sides of the first isolation cell.

Abstract: A semiconductor device includes a substrate, a first gate structure, a second gate structure, a third gate structure, and a first source/drain region. The first, second, and third gate structures are above the substrate and arranged in a first direction. The first, second, and third gate structures extend in a second direction different from the first direction, and the second gate structure is between the first and third gate structures. The first source/drain region is between the first and third gate structures, and the first source/drain region is at one end of the second gate structure.

Abstract: A circuit includes a selection circuit configured to receive a first address from a first port and a second address from a second port, a first latch circuit coupled to the selection circuit and configured to output each of the first address and the second address received from the selection circuit, a decoder, and a control circuit. The control circuit is configured to generate a plurality of signals configured to cause the decoder to decode each of the first address and the second address.

Abstract: An integrated circuit comprising an n-type drift region, a gate structure directly on a first portion of the n-type drift region, a drain structure formed in a second portion of the n-type drift region, the gate structure and the drain structure being separated by a drift region length, a resist protective oxide (RPO) formed over a portion of the n-type drift region between the gate structure and the drain structure, a field plate contact providing a direct electrical connection to the resist protective oxide.

Abstract: A circuit includes a bias circuit and a level shifter. The bias circuit includes first and second input terminals configured to receive first and second power supply voltages, and is configured to generate a bias voltage having the greater of a first voltage level of the first power supply voltage or a second voltage level of the second power supply voltage. The level shifter includes a first PMOS transistor configured to receive the first power supply voltage and a second PMOS transistor configured to receive the second power supply voltage, and each of the first and second PMOS transistors includes a bulk terminal configured to receive the bias voltage.

Abstract: A memory device includes a first plurality of program lines of a first group, a second plurality of program lines of a second group, and a plurality of address lines. The second plurality of program lines are disposed next to and are parallel to the first plurality of program lines. The plurality of address lines are coupled to the first plurality of program lines and the second plurality of program lines respectively. The plurality of address lines are twisted and are intersected with the first plurality of program lines and the second plurality of program lines in a layout view. At least two adjacent program lines of the first plurality of program lines or the second plurality of program lines have lengths different from each other. A method is also disclosed herein.

Abstract: A device is disclosed herein. The device includes an electrostatic discharge (ESD) protection switch and an ESD driver. The ESD driver is configured to receive a first voltage and a second voltage. When a voltage difference between the first voltage and the second voltage is higher than a first voltage threshold, the ESD driver outputs a first trigger signal to turn on the ESD protection switch. When the voltage difference between the first voltage and the second voltage is lower than a second voltage threshold, the ESD driver outputs a second trigger signal to turn on the ESD protection switch.

Abstract: A device includes a transistor, an insulating structure, a buried conductive line, and a buried via. The transistor is above a substrate and includes a source/drain region and a source/drain contact above the source/drain region. The insulating structure is above the substrate and laterally surrounds the transistor. The buried conductive line is in the insulating structure and spaced apart from the transistor. The buried via is in the insulating structure and interconnects the transistor and the buried conductive line. A height of the buried conductive line is greater than a height of the source/drain contact.

Abstract: A memory device includes a word line driver. The word line driver is coupled through word lines to an array of bit cells. The word line driver includes a first driving circuit, a second driving circuit and a modulating circuit. The first driving circuit and the second driving circuit are configured to select a word line. The modulating circuit is coupled through the selected word line to the first driving circuit and the second driving circuit, and is configured to modulate at least one signal transmitted through the selected word line. The first driving circuit and the second driving circuit are further configured to charge the selected word line to generate a first voltage signal and a second voltage signal at two positions of the selected word line. The first voltage signal is substantially the same as the second voltage signal. A method is also disclosed herein.

Abstract: A circuit includes a first inverter, a second inverter, a first header circuit and a second header circuit. The first inverter is configured to convert a first global write signal into a first local write signal transmitted to a complement bit line. The second inverter is configured to convert a second global write signal into a second local write signal transmitted to a bit line. The first header circuit connects or disconnects a power terminal of the first inverter with a positive reference voltage supply in response to a write enable signal and the second global write signal. The second header circuit connects or disconnects a power terminal of the second inverter with the positive reference voltage supply in response to a write enable signal and the first global write signal.

Abstract: A semiconductor device includes a source/drain region, a body region, a first gate structure, and a second gate structure. The source/drain region and the body region are in a substrate. The first and second gate structures are above the substrate. The source/drain region and the body region are on opposite sides of the first gate structure. The second gate structure is spaced apart from the first gate structure. The source/drain region, the body region, and the first gate structure are on a same side of the second gate structure.