Abstract: A semiconductor device includes a source/drain region, a body region, a first gate structure, and a second gate structure. The source/drain region and the body region are in a substrate. The first and second gate structures are above the substrate. The source/drain region and the body region are on opposite sides of the first gate structure. The second gate structure is spaced apart from the first gate structure. The source/drain region, the body region, and the first gate structure are on a same side of the second gate structure.

Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.

Abstract: A semiconductor device includes a semiconductor substrate, a deep n-well, a field oxide, a gate structure, a p-type doped region, a source region, and a drain region. The deep n-well is in the semiconductor substrate. The field oxide is partially embedded in the deep n-well and having a tip corner in a position substantially level with a top surface of the semiconductor substrate. The gate structure is on the field oxide and laterally extends past the tip corner of the field oxide. The p-type doped region is in the deep n-well and is interfaced with the tip corner of the field oxide. The source region and a drain region are laterally separated at least in part by the p-type doped region and the field oxide.

Abstract: A circuit includes a first inverter, a second inverter, a first header circuit and a second header circuit. The first inverter is configured to convert a first global write signal into a first local write signal transmitted to a complement bit line. The second inverter is configured to convert a second global write signal into a second local write signal transmitted to a bit line. The first header circuit connects or disconnects a power terminal of the first inverter with a positive reference voltage supply in response to a write enable signal and the second global write signal. The second header circuit connects or disconnects a power terminal of the second inverter with the positive reference voltage supply in response to a write enable signal and the first global write signal.

Abstract: An integrated circuit includes a plurality of memory cells, a first pair of complementary data lines, and a second pair of complementary data lines. The plurality of memory cells include a first array of memory cells and a second array of memory cells. The first pair of complementary data lines are coupled to the first array of memory cells. The second pair of complementary data lines are different from the first pair of complementary data lines and are coupled to the second array of memory cells. A number of memory cells in the first array of memory cells is different from a number of memory cells in the second array of memory cells.

Abstract: A device includes a voltage regulator circuit, a power switch circuit, and a control circuit. The voltage regulator circuit generates an output voltage at an output terminal. The power switch circuit is coupled to the voltage regulator circuit. The control circuit receives a first control signal and generates a second signal that includes a first portion gradually declining between a first time and a second time later than the first time. When the voltage regulator circuit is turned off and a logic state of the first control signal changes at the first time, the power switch circuit is turned on at the second time, in response to the second control signal, to adjust the output voltage.

Abstract: An integrated circuit includes multiple memory cells, a first pair of complementary data lines, a second pair of complementary data lines, multiple first word lines, and multiple second word lines. The memory cells include a first array of memory cells and a second array of memory cells. The first pair of complementary data lines are coupled to the first array of memory cells. The second pair of complementary data lines are coupled to the second array of memory cells. Lengths of the first pair of complementary data lines are shorter than lengths of the second pair of complementary data lines. The first word lines and the second word lines are arranged according to a predetermined ratio of a number of the first word lines to a number of the second word lines. The predetermined ratio is less than 1.

Abstract: An integrated circuit includes a pull-up circuit, an electrostatic discharge (ESD) primary circuit, and a pull-down circuit. The pull-up circuit is coupled between a pad and a first voltage terminal. The ESD primary circuit includes a first terminal which is coupled to the pad and the pull-up circuit, and a second terminal coupled to a second voltage terminal different from the first voltage terminal. The pull-down circuit has a first terminal which is coupled to the pad, the ESD primary circuit and the pull-up circuit, and a second terminal coupled to the second voltage terminal. The pull-down circuit includes at least one first transistor of a first conductivity type having a first terminal coupled to the first terminal of the pull-down circuit. A breakdown voltage of the at least one first transistor is greater than a trigger voltage of the ESD primary circuit.

Abstract: A semiconductor device includes a gate structure, a double diffused region, a source region, a drain region, a first gate spacer, and a second gate spacer. The gate structure is over a semiconductor substrate. The double diffused region is in the semiconductor substrate and laterally extends past a first side of gate structure. The source region is in the semiconductor substrate and is adjacent a second side of the gate structure opposite the first side. The drain region is in the double diffused region in the semiconductor substrate and is of a same conductivity type as the double diffused region. The first gate spacer is on the first side of the gate structure. The second gate spacer extends upwardly from the double diffused region along an outermost sidewall of the first gate spacer and terminates prior to reaching a top surface of the gate structure.

Abstract: A method includes forming a gate structure over a substrate; forming a first gate spacer and a second gate spacer on opposite sidewalls of the gate structure, respectively; implanting a first dopant of a first conductivity type into the substrate form a lightly doped source region adjacent to the first gate spacer, and a lightly doped drain region adjacent to the second gate spacer; forming a patterned mask over a first portion of the lightly doped drain region, while leaving a second portion of the lightly doped drain region exposed; and with the patterned mask in place, implanting a second dopant of the first conductivity type into the substrate, resulting in converting the second portion of the lightly doped drain region into a drain region.

Abstract: A circuit includes a tracking word line, a power switch, a tracking bit line, a sense circuit. The power switch is coupled between the tracking word line and a first node. The power switch is configured to discharge a voltage level on the first node in response to a clock pulse signal transmitted through the tracking word line to the power switch. The tracking bit line is coupled between the first node and a plurality of tracking cells in a memory array. The sense circuit is coupled between the first node and a second node. The sense circuit is configured to generate a negative bit line enable signal in response to that the voltage level on the first node is below a threshold voltage value of the sense circuit.

Abstract: A memory device includes a first isolation cell, a first memory array of a first memory segment, a second memory array of a second memory segment, a first decoder cell of the first memory segment and a second decoder cell of the second memory segment. The first isolation cell extends in a first direction. The first memory array of the first memory segment abuts a first boundary of the first isolation cell in a second direction different from the first direction. The second memory array of the second memory segment abuts a second boundary, opposite to the first boundary, of the first isolation cell in the second direction. The first decoder cell of the first memory segment and the second decoder cell of the second memory segment are arranged on opposite sides of the first isolation cell.

Abstract: A method of forming a semiconductor structure including: forming a drift well in a substrate, in which the drift well includes first dopants having a first conductivity type; forming an isolation structure over the drift well; forming a well region in the drift well and spaced apart from the isolation structure, such that a top portion of the drift well is between the well region and the isolation structure; doping the top portion with second dopants having a second conductivity type different from the first conductivity type, such that a doping concentration of the second dopants in the top portion is lower than a doping concentration of the first dopants in the top portion after doping the top portion; and forming a gate structure extending from the isolation structure to the well region and covering the top portion of the drift well.

Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.

Abstract: A semiconductor device includes substrate, a first gate structure, a second gate structure, and an epitaxy layer. The first gate structure and the second gate structure are over the substrate, in which the first gate structure and the second gate structure each comprises a shielding electrode, a gate electrode over the shielding electrode, and a first gate dielectric layer vertically separating the shielding electrode from the gate electrode. The epitaxy layer is over the substrate and cups an underside of the first gate structure and the second gate structure, in which the epitaxy layer comprises a doped region laterally between the first gate dielectric layer of the first gate structure and the first gate dielectric layer of the second gate structure, a dopant concentration of the doped region being non-uniform along a lateral direction.

Abstract: A device includes memory banks, a first pair of write data wirings, a second pair of write data wirings and a global write circuit. The first pair of write data wirings is connected to a first group among the memory banks. The second pair of write data wirings is connected to a second group among the memory banks. In response to a first clock signal, the global write circuit generates a first global write signal and a first complement global write signal transmitted to the first group among the memory banks through the first pair of write data wirings. In response to a second clock signal, the global write circuit generates a second global write signal and a second complement global write signal transmitted to the second group among the memory banks through the second pair of write data wirings.

Abstract: An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.

Abstract: An IC structure includes first and second gates, first and second source/drain regions, and an isolation region. The first and second gates each have a first portion extending along a first direction and a second portion extending along a second direction. The first source/drain regions are respectively on opposite sides of the first portion of the first gate. The second source/drain regions are respectively on opposite sides of the first portion of the second gate. The isolation region has a lower portion between a first one of the first source/drain regions and a first one of the second source/drain regions, and an upper portion partially overlapping with the second portion of first gate and the second portion of the second gate. A width of the lower portion is a less than a width of the upper portion.

Abstract: An integrated circuit includes a control circuit, a first voltage generation circuit, and a second voltage generation circuit. The control circuit is coupled between a first voltage terminal and a first node, and generates an initiation voltage at the first node. The first voltage generation circuit and the second voltage generation circuit are coupled to a first capacitive unit at the first node and coupled to a second capacitive unit at a second node. The first voltage generation circuit generates, in response to the initiation voltage at the first node, a first control signal based on a first supply voltage to the second voltage generation circuit. The second voltage generation circuit generates, in response to the first control signal received from the first voltage generation circuit, a second control signal to the first node, based on a second supply voltage.

Abstract: A device is disclosed. The device includes a first tracking control line, a first tracking circuit, a first sense circuit, and a precharge circuit. The first tracking control line is configured to transmit a first tracking control signal. The first tracking circuit is configured to generate, in response to the first tracking control signal, a first tracking signal associated with first tracking cells in a memory array. The first sense circuit is configured to receive the first tracking signal, and is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge of the first sense tracking signal and a falling edge of a read enable delayed signal, a precharge signal for precharging data lines associated with memory cell in the memory array. A method is also disclosed herein.