Abstract: A multi-wafer stacking structure and fabrication method are disclosed. In the multi-wafer stacking structure, a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.

Abstract: A voltage detection circuit for a charge pump is disclosed. The voltage detection circuit includes a sampling circuit and a latch circuit. The sampling circuit is configured to sample a supply voltage and provide the latch circuit with a sampled voltage. The latch circuit is configured to detect the sampled voltage and latch a result of the detection. And the latch circuit is connected to a voltage regulation circuit which is configured to regulate a charge-pump cascade structure in the charge pump based on the result of the detection so as to maintain an output voltage of the charge pump stable.

Abstract: A sensor device includes a first wafer structure and a second wafer structure bonded to the first wafer structure. The first wafer structure includes a first substrate, an integrated circuit layer integrated with the first substrate, and a three-dimensional (3D) NAND memory cell array integrated with the integrate circuit layer. The integrated circuit layer and the 3D NAND memory cell array are located at the same side of the first substrate. The second wafer structure includes a second substrate and a sensing module of a sensor integrated with the second substrate. A manufacturing method of the sensor device includes bonding the second wafer structure to the first wafer structure. A side of the first wafer structure where the 3D NAND memory cell array is located is bonded to a side of the second wafer structure where the sensing module is located.

Abstract: A charge pump drive circuit is disclosed. The charge pump drive circuit includes a first pulse generating circuit and a second pulse generating circuit. Each of the first pulse generating circuit and the second pulse generating circuit is configured to connect to a charge pump. The first pulse generating circuit is configured to provide the charge pump with a series of first pulse signals. The second pulse generating circuit is configured to generate a second pulse signal in response to and based on an address translation detection signal and provide the second pulse signal to the charge pump or to the first pulse generating circuit. The first pulse generating circuit generates an additional first pulse signals based on the second pulse signal.

Abstract: A circuit for regulating a leakage current in a charge pump is disclosed. The circuit includes a bias voltage generating circuit and a first transistor, wherein: the bias voltage generating circuit generates a bias voltage that is proportional to a supply voltage; a gate of the first transistor is coupled to the bias voltage; the first transistor has a drain that is coupled to an output of the charge pump and a source that is grounded; a voltage the drain of the first transistor is proportional to the supply voltage; and a current flowing through the source and drain of the first transistor is proportional to the supply voltage that powers the charge pump.

Abstract: A method for alleviating an etching defect of a salicide barrier layer is disclosed. The salicide barrier layer includes a first barrier layer, a second barrier layer and a third barrier layer. When the salicide barrier layer is being etched, the third barrier layer is removed during first etching. In this case, the second barrier layer is used as an etch stop layer, and the second barrier layer is removed during second etching. In this case, the first barrier layer is used as an etch stop layer, the first barrier layer is removed during third etching. The salicide barrier layer is divided into three layers, the second barrier layer and the first barrier layer are respectively used as an etch stop layer, so that the third barrier layer and the second barrier layer can be prevented from being over-etched, thereby effectively avoiding defects caused by over-etching and alleviating device performance.

Abstract: A sensing circuit includes a plurality of cascode transistors including: a Flash memory cell; a sensing node; and an NMOS. The sensing circuit further includes a charge pump for generating an output voltage. A first output voltage is directly input to the plurality of cascode transistors during programming, and a second output voltage of the charge pump is coupled to a gate of the NMOS during a read to bias the NMOS. A sensing amplifier has an input coupled to the sensing node for receiving read data of the Flash memory cell when the NMOS is biased. A low-pass filter is coupled between the second output voltage of the charge pump and the gate of the NMOS.

Abstract: A voltage regulator includes a first feedback loop and a second feedback loop. The first feedback loop includes a charge pump outputting a first output voltage, a first transistor ladder and a control circuit. The first transistor ladder divides the first output voltage to generate a first feedback voltage. The control circuit receives the first feedback voltage and controls a level of the first output voltage according to the first feedback voltage and a reference voltage. The second feedback loop includes a power transistor, a second transistor ladder and an operational amplifier. The power transistor receives the first output voltage to output a second output voltage. The second transistor ladder divides the second output voltage to generate a second feedback voltage. The operational amplifier outputs a control signal to the power transistor by receiving the second feedback voltage and a reference voltage selected from one of a plurality of levels.

Abstract: A two-sided memory array is disclosed. Each side includes four local x-decoders. Each local x-decoder includes: a first pair of cascode transistors coupled to a first signal; a second pair of cascode transistors coupled to the first signal, a second signal, and a word line; a third transistor coupled to the first signal; and a third pair of cascode transistors coupled to the second signal, a third signal, and the word line. All transistors in each local x-decoder are disposed vertically, and P-channels and N-channels on each side of the memory array are disposed in an order corresponding to P-channels of a first local x-decoder, P-channels of a second local x-decoder, P-channels of a third local x-decoder, P-channels of a fourth local x-decoder, N-channels of the fourth local x-decoder, N-channels of the third local x-decoder, N-channels of the second local x-decoder and N-channels of the first local x-decoder.

Abstract: A local X-decoder for a memory system includes a decoding unit configured to generate a word line signal to a memory cell of a memory array of the memory system; and an unselected erase detecting unit coupled to the decoding unit, and configured to increase an absolute voltage coupled to the word line signal from a well of the memory cell according to an unselected erase mode signal generated by an erase mode decoder of the memory system; wherein the word line signal is floating to a same level as the well of the memory cell when the memory cell is unselected in an erase mode of the memory system.

Abstract: A low drop-out (LDO) regulator including a first operational amplifier, a first transistor, a second transistor, a voltage feedback circuit and a charge pump is disclosed. Each of the first transistor and the second transistor is coupled between supply voltage and an output voltage. The first operational amplifier outputs a first gate-controlled voltage to turn the first transistor on or off. A second gate-controlled voltage is provided to the second transistor to turn it on or off. The charge pump makes the second gate-controlled voltage equal to the sum of the output voltage, a threshold voltage of the second transistor and a drive voltage of the second transistor. The voltage feedback circuit provides a feedback voltage to the first operational amplifier. The first gate-controlled voltage is positively correlated to the feedback voltage. The first transistor is a P-channel field effect transistor; the second transistor is an N-channel field effect transistor.

Abstract: A charge pump system includes: a differential amplifier, for receiving a feedback voltage and a reference voltage and generating an output signal; an oscillating circuit for generating clock pulses; a charge pump for receiving the clock pulses and generating an output voltage; a current sink coupled to the output of the charge pump; a first pair of cascode transistors for generating a digital signal; and an inverter for inverting the digital signal to generate a first digital signal according to the output signal, wherein the first digital signal is input to the current sink. When the feedback voltage is higher than the reference voltage, the first digital signal will be generated and the current sink will be turned on, and when the feedback voltage is lower than the reference voltage, the first digital signal will not be generated and the current sink will be turned off.

Abstract: The invention provides a semiconductor cooling method that comprises: providing two wafers which require to be treated by a mixed bonding process, wherein each of the wafers being provided with several metallic device structure layers therein. A heat dissipation layer is set in at least one of the wafers and arranged in the free area above at least one of the metallic device structure layers, and the heat dissipation layer connects to the adjacent metallic device structure layer and the invention provides a method of heat dissipation that comprises providing at least two wafers to be bonded; and arranging some conducting wires on a surface of wafers. In addition, the method includes the steps of performing a bonding process to form a device with bonded wafers, wherein one end of the conducting wires locates in the region where the wafers generate heat, and another end extends to an external of wafers.

Abstract: The invention relates to a field of semiconductor manufacturing technology, more particularly, to a method for preparing three-dimensional integrated inductor-capacitor structure, which can realize the inductor-capacitor of three-dimensional structure, and form three-dimensional spiral inductor centering on the magnetic cores of single direction around through the preparation of the interconnected top metal conducting wires and bottom metal conducting wires, which can gain capacitance and inductance at the same time in a relatively small space, and reduce the production costs, and also greatly improves the inductance magnetic flux in order to increase the inductance value and reduce eddy current, and improve the quality factor Q value and the performance of inductance coil.

Abstract: The invention relates to the field of semiconductor, more particularly, to a preparation process of image sensors, comprising: Step S1, providing a semiconductor structure, a top of which is provided with a groove, and leads being formed in said groove, the top of said semiconductor structure and an exposed surface of said groove are covered with a first dielectric layer; Step S2: depositing a second dielectric layer covering the upper surface of said first dielectric layer and said leads and filling said groove; Step S3: performing a reversed-etching process to thin said second dielectric layer, and to form a convex structure on a surface of said second dielectric layer above the groove; Step S4: performing a planarization process to said second dielectric layer to improve surface evenness of said second dielectric layer after grinding by the convex structure.