Intel Patents Granted

Patents granted to Intel by the U.S. Patent and Trademark Office (USPTO).

  • Package-integrated multi-turn coil embedded in a package magnetic core
    Patent number: 11955426
    Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Huong Do, Kaladhar Radhakrishnan, Krishna Bharath, Yikang Deng, Amruthavalli P. Alur
  • System, apparatus and method for configurable control of asymmetric multi-threading (SMT) on a per core basis
    Patent number: 11953962
    Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Daniel J. Ragland, Guy M. Therien, Ankush Varma, Eric J. DeHaemer, David T. Mayo, Ariel Gur, Yoav Ben-Raphael, Mark P. Seconi
  • Interposer structures and methods for 2.5D and 3D packaging
    Patent number: 11955431
    Abstract: Semiconductor packages, and methods for making the semiconductor packages, having an interposer structure with one or more interposer and an extension platform, which has an opening for placing the interposer, and the space between the interposer and the extension platform is filled with a polymeric material to form a unitary interposer-extension platform composite structure. A stacked structure may be formed by at least a first semiconductor chip coupled to the interposer and at least a second semiconductor chip coupled to the extension platform, and at least one bridge extending over the space that electrically couples the extension platform and the interposer. The extension platform may include a recess step section that may accommodate a plurality of passive devices to reduced power delivery inductance loop for the high-density 2.5D and 3D stacked packaging applications.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Jenny Shio Yin Ong, Seok Ling Lim, Bok Eng Cheah, Jackson Chung Peng Kong, Saravanan Sethuraman
  • Technologies for dynamically sharing remote resources across remote computing nodes
    Patent number: 11954528
    Abstract: Technologies for dynamically sharing remote resources include a computing node that sends a resource request for remote resources to a remote computing node in response to a determination that additional resources are required by the computing node. The computing node configures a mapping of a local address space of the computing node to the remote resources of the remote computing node in response to sending the resource request. In response to generating an access to the local address, the computing node identifies the remote computing node based on the local address with the mapping of the local address space to the remote resources of the remote computing node and performs a resource access operation with the remote computing node over a network fabric. The remote computing node may be identified with system address decoders of a caching agent and a host fabric interface. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Daniel Rivas Barragan, Alejandro Duran Gonzalez, Harald Servat
  • Lined photobucket structure for back end of line (BEOL) interconnect formation
    Patent number: 11953826
    Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: James M. Blackwell, Robert L. Bristol, Marie Krysak, Florian Gstrein, Eungnak Han, Kevin L. Lin, Rami Hourani, Shane M. Harlson
  • Wireless communication technology, apparatuses, and methods
    Patent number: 11955732
    Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Brandon Davis, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Yossi Tsfati, Marian Verhelst, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
  • Architecture to manage FLI bump height delta and reliability needs for mixed EMIB pitches
    Patent number: 11955448
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate and a bridge substrate embedded in the package substrate. In an embodiment, first pads are over the package substrate, where the first pads have a first pitch, and second pads are over the bridge substrate, where the second pads have a second pitch that is smaller than the first pitch. In an embodiment, a barrier layer is over individual ones of the second pads. In an embodiment, reflown solder is over individual ones of the first pads and over individual ones of the second pads. In an embodiment, a first standoff height of the reflown solder over the first pads is equal to a second standoff height of the reflown solder over the second pads.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Jung Kyu Han, Hongxia Feng, Xiaoying Guo, Rahul N. Manepalli
  • Technologies for a high-voltage transmission gate
    Patent number: 11955965
    Abstract: Technologies for a high-voltage transmission gate are disclosed. In the illustrative embodiment, a companion chip is connected to a quantum processor. The companion chip provides voltages to gates of qubits on the quantum processor. The companion chip includes one or more high-voltage transmission gates that can be used to charge capacitors linked to gates of qubits on the quantum processor. The transmission gate includes transistors with a breakdown voltage less than a range of input and output voltages of the transmission gate. Control circuitry on the companion chip controls the voltages applied to transistors of the transmission gate to ensure that the voltage differences across the terminals of each transistor is below a breakdown voltage.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Sushil Subramanian, Stefano Pellerano, Todor Mladenov, JongSeok Park, Bishnu Prasad Patra
  • Source or drain structures with high phosphorous dopant concentration
    Patent number: 11955482
    Abstract: Integrated circuit structures having high phosphorous dopant concentrations are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each of the epitaxial structures of the first and second source or drain structures includes silicon and phosphorous, the phosphorous having an atomic concentration in a core region of the silicon greater than an atomic concentration in a peripheral region of the silicon.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Robert Ehlert, Timothy Jen, Alexander Badmaev, Shridhar Hegde, Sandrine Charue-Bakker
  • Stackable in-line filter modules for quantum computing
    Patent number: 11957066
    Abstract: Embodiments of the present disclosure describe quantum circuit assemblies that include one or more filter modules integrated in a package with a quantum circuit component having at least one qubit device. Integration may be such that both the quantum circuit component and the filter module(s) are at least partially inside a chamber formed by a radiation shield structure that is configured to attenuate electromagnetic radiation incident on the quantum circuit component and the filter module(s). Placing filter modules under the protection provided by the radiation shield structure may boost coherence of the qubits. Some example filter modules may include filter(s) configured to convert electromagnetic radiation to heat and filter(s) configured to perform bandpass filtering. Modular blocks of in-line filters inside the shielded environment may allow to route signals to the quantum circuit component with reduced noise and speed up installation of a complete quantum computer.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Florian Luthi, Lester Lampert
  • Passivation layers for thin film transistors and methods of fabrication
    Patent number: 11955560
    Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Arnab Sen Gupta, Travis W. LaJoie, Sarah Atanasov, Chieh-Jen Ku, Bernhard Sell, Noriyuki Sato, Van Le, Matthew Metz, Hui Jae Yoo, Pei-Hua Wang
  • Methods and apparatus for machine learning-guided compiler optimizations for register-based hardware architectures
    Patent number: 11954466
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that perform machine learning-guided compiler optimizations for register-based hardware architectures. Examples disclosed herein include a non-transitory computer readable medium comprising instructions that, when executed, cause a machine to at least select a register-based compiler transformation to apply to source code at a current position in a search tree, determine whether the search tree is in need of pruning based on an output of a query to a machine learning (ML) model, in response to determining the search tree is in need of pruning, prune the search tree at the current position, in response to applying the selected register-based compiler transformation to the source code, generate a code variant, calculate a score associated with the source code at the current position in the search tree, and update parameters of the machine learning (ML) model to include the calculated score.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Anand Venkat, Justin Gottschlich, Niranjan Hasabnis
  • Components for millimeter-wave communication
    Patent number: 11955684
    Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Diego Correas-Serrano, Georgios Dogiamis, Henning Braunisch, Neelam Prabhu Gaunkar, Telesphor Kamgaing
  • Object and cacheline granularity cryptographic memory integrity
    Patent number: 11954045
    Abstract: Technologies disclosed herein provide one example of a system that includes processor circuitry and integrity circuitry. The processor circuitry is to receive a first request associated with an application to perform a memory access operation for an address range in a memory allocation of memory circuitry. The integrity circuitry is to determine a location of a metadata region within a cacheline that includes at least some of the address range, identify a first portion of the cacheline based at least in part on a first data bounds value stored in the metadata region, generate a first integrity value based on the first portion of the cacheline, and prevent the memory access operation in response to determining that the first integrity value does not correspond to a second integrity value stored in the metadata region.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: David M. Durham, Michael LeMay, Santosh Ghosh, Sergej Deutsch
  • Differential on-chip loop antenna
    Patent number: 11955728
    Abstract: Aspects of the embodiments are directed to an on-chip loop antenna and methods of manufacturing the same. In some embodiments, the on-chip loop antenna is in an integrated circuit (IC) die. The IC die comprises metal loops substantially centered around a core region of the IC die in a metallization stack of the IC die, a dielectric between spaces of the metal loops, an electric circuit in the core region electrically connected to the metal loops with an interconnect, and a ground plane in the metallization stack electrically connected to the loops with a first plurality of vias and to the electric circuit with a second plurality of vias. The first plurality of vias is different from the second plurality of vias, and the electric circuit includes an inductor. In some embodiments, the on-chip loop antenna can be carried by a semiconductor package.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Nir Weisman, Omer Asaf, Eyal Goldberger
  • Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format
    Patent number: 11954063
    Abstract: Described herein is a graphics processing unit (GPU) configured to receive an instruction having multiple operands, where the instruction is a single instruction multiple data (SIMD) instruction configured to use a bfloat16 (BF16) number format and the BF16 number format is a sixteen-bit floating point format having an eight-bit exponent. The GPU can process the instruction using the multiple operands, where to process the instruction includes to perform a multiply operation, perform an addition to a result of the multiply operation, and apply a rectified linear unit function to a result of the addition.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Subramaniam Maiyuran, Shubra Marwaha, Ashutosh Garg, Supratim Pal, Jorge Parra, Chandra Gurram, Varghese George, Darin Starkey, Guei-Yuan Lueh
  • Ultra small molded module integrated with die by module-on-wafer assembly
    Patent number: 11955434
    Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Yoshihiro Tomita, Eric J. Li, Shawna M. Liff, Javier A. Falcon, Joshua D. Heppner
  • Apparatus, method, and system for collecting cold pages
    Patent number: 11954356
    Abstract: Apparatus, method, and system for efficiently identifying and tracking cold memory pages are disclosed. The apparatus in one embodiment includes one or more processor cores to access memory pages stored in the memory by issuing access requests to the memory and a page index bitmap to track accesses made by the one or more processor cores to the memory pages. The tracked accesses are usable to identify infrequently-accessed memory pages, where the infrequently-accessed memory pages are removed from the memory and stored in a secondary storage.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Qiuxu Zhuo, Anthony Luck
  • Technology to provide accurate training and per-bit deskew capability for high bandwidth memory input/output links
    Patent number: 11954360
    Abstract: Systems, apparatuses and methods may provide for technology that programs a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word (DWORD) and at least two of the plurality of seed values differ from one another. The technology may also train a link coupled to the plurality of LFSRs, wherein the plurality of seed values cause a parity bit associated with the DWORD to toggle while the link is being trained. In one example, the technology also automatically selects the plurality of seed values based on one or more of an expected traffic pattern on the link (e.g., after training) or a deskew constraint associated with the link.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Narasimha Lanka, Kuljit Bains, Lohit Yerva
  • Dual metal gate structure having portions of metal gate layers in contact with a gate dielectric
    Patent number: 11955532
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Jeffrey S. Leib, Jenny Hu, Anindya Dasgupta, Michael L. Hattendorf, Christopher P. Auth
  • Subtractive etch resolution implementing a functional thin metal resist
    Patent number: 11948848
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Jeremy Ecton, Oscar Ojeda, Leonel Arana, Suddhasattwa Nad, Robert May, Hiroki Tanaka, Brandon C. Marin
  • End-to-end data protection for far memory data transfer from host to media
    Patent number: 11947995
    Abstract: A multilevel memory system includes a nonvolatile memory (NVM) device with an NVM media having a media write unit that is different in size than a host write unit of a host controller of the system that has the multilevel memory system. The memory device includes a media controller that controls writes to the NVM media. The host controller sends a write transaction to the media controller. The write transaction can include the write data in host write units, while the media controller will commit data in media write units to the NVM media. The media controller can send a transaction message to indicate whether the write data for the write transaction was successfully committed to the NVM media.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Kuan Hua Tan, Sahar Khalili, Eng Hun Ooi, Shrinivas Venkatraman, Dimpesh Patel
  • Transmitter and method for generating radio frequency transmit signal, mobile device and base station
    Patent number: 11949441
    Abstract: A transmitter for generating a radio frequency, RF, transmit signal is provided. The transmitter includes signal generation circuitry configured to generate, based on a sequence of first control words each indicating a respective frequency shift with respect to a target frequency of the RF transmit signal, a RF carrier signal with sequentially varying frequency over time in order to frequency spread the RF transmit signal. Further, the transmitter includes modulation circuitry configured to generate the RF transmit signal by modulating the RF carrier signal with a modulation control signal. The transmitter additionally includes modification circuitry configured to generate the modulation control signal by modifying, based on the sequence of first control words, phase information of a baseband signal bearing information to be transmitted or phase information of a signal derived from the baseband signal in order to frequency de-spread the RF transmit signal.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Elan Banin, Ofir Degani, Rotem Banin, Shahar Gross
  • Technologies for multiple device authentication in a heterogeneous network
    Patent number: 11949780
    Abstract: A disclosed example gateway node includes network communicator circuitry, memory, instructions, and processor circuitry. The network communicator circuitry is to send a first portion of a multi-part secret key to a first secret holder node, and send a plurality of shares of a second portion of the multi-part secret key to second secret holder nodes. The processor circuitry is to execute the instructions to combine responses from the first secret holder node and at least one of the second secret holder nodes to generate a combined authentication message, the network communicator circuitry to send the combined authentication message to a terminal node for authentication.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Alexandra Afanasyeva, Sergey Bezzateev, Vitaly Petrov, Konstantin Zhidanov, Natalia Voloshina, Vladimir Zybin, Anna Bakunova
  • Trench contact structures for advanced integrated circuit structure fabrication
    Patent number: 11948997
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Subhash M. Joshi, Jeffrey S. Leib, Michael L. Hattendorf
  • Increased utilization of wireless frequency channels partially occupied by incumbent systems
    Patent number: 11949606
    Abstract: A wireless communication device, method and system. The device includes a memory, and a processing circuitry coupled to the memory. The processing circuitry is to: decode at least one signal field portion of a signal field of a Physical Layer Convergence Protocol (PLCP) Data Unit (PPDU) received over a bonded channel, the bonded channel comprising a plurality of subchannels including a punctured subchannel, the signal field portion on at least one unpunctured subchannel of the plurality of subchannels; determine, from the at least one signal field portion, information on a resource allocation for the device, the resource allocation indicating at least one resource unit (RU) used in a data field of the PPDU for the device; and decode a data field portion of the data field of the PPDU, the data field portion received on a part of the punctured subchannel based on the resource allocation.
    Type: Grant
    Filed: October 24, 2022
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Laurent Cariou, Xiaogang Chen, Qinghua Li, Robert J. Stacey, Huaning Niu
  • Etch barrier for microelectronic packaging conductive structures
    Patent number: 11948898
    Abstract: Conductive structures in a microelectronic package and having a surface roughness of 50 nm or less are described. This surface roughness is from 2 to 4 times less than can be found in packages with conductive structures (e.g., traces) formed using alternative techniques. This reduced surface roughness has a number of benefits, which in some cases includes a reduction of insertion loss and improves a signal to noise ratio for high frequency computing applications. The reduced surface roughness can be accomplished by protecting the conductive structure r during etch processes and applying an adhesion promoting layer to the conductive structure.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Srinivas V. Pietambaram, Hongxia Feng, Xiaoying Guo, Benjamin T. Duong
  • Reflection routing as a framework for adaptive modular load balancing for multi-hierarchy network on chips
    Patent number: 11949595
    Abstract: An apparatus includes a first set of processing element nodes, the first set of processing element nodes defining a first hierarchy of processing element nodes, the first set of processing element nodes comprising a source node, a first look-up table (LUT), and a first forwarder node, the source node to communicate with the first forwarder node by a first virtual channel. The apparatus includes a second set of processing element nodes, the second set of processing element nodes defining a second hierarchy of processing element nodes, the second set of processing element nodes comprising a second forwarder node, a second LUT, the second LUT comprising an indication of a direction of the first forwarder node in the first hierarchy, and a target node logically coupled to the second forwarder node by the first virtual channel. The first LUT comprises a direction of the second forwarder node in the second hierarchy.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Yonatan Meir Levitt, Gaspar Mora Porta
  • In-place memory copy during remote data transfer in heterogeneous compute environment
    Patent number: 11947801
    Abstract: An apparatus to facilitate in-place memory copy during remote data transfer in a heterogeneous compute environment is disclosed. The apparatus includes a processor to receive data via a network interface card (NIC) of a hardware accelerator device; identify a destination address of memory of the hardware accelerator device to write the data; determine that access control bits of the destination address in page tables maintained by a memory management unit (MMU) indicate that memory pages of the destination address are both registered and free; write the data to the memory pages of the destination address; and update the access control bits for memory pages of the destination address to indicate that the memory pages are restricted, wherein setting the access control bits to restricted prevents the NIC and a compute kernel of the hardware accelerator device from accessing the memory pages.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: April 2, 2024
    Assignee: INTEL CORPORATION
    Inventors: Reshma Lal, Sarbartha Banerjee
  • Gaze-attenuated virtual desktop
    Patent number: 11947108
    Abstract: Methods, systems and apparatuses may provide for technology that renders a plurality of virtual monitors to a head mounted display (HMD), detects a change in gaze direction with respect to the HMD, and conducts a modification of one or more of a refresh rate or a texture capture rate associated with at least one of the plurality of virtual monitors based on the change in gaze direction.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: William Hux, Mario Palumbo
  • Technologies for out-of-order network packet management and selective data flow splitting
    Patent number: 11949576
    Abstract: Technologies for providing out-of-order network packet management and selective data flow splitting include a computing device. The computing device includes circuitry to identify a service data flow associated with a set of packets to be sent to a recipient computing device. The circuitry is also to determine a target quality of service for the service data flow, determine, as a function of the target quality of service, one or more radio links on which to send the packets, including determining whether to split the service data flow over multiple radio links, and send the packets through the determined one or more radio links.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Ahmed Soud Salem, Jerome Parron
  • Controller for an autonomous vehicle, and network component
    Patent number: 11947357
    Abstract: A controller for an autonomous vehicle may include: one or more processors configured to: determine a maneuver planned for the vehicle based on a safety driving model and based on a first message from a network component external to the vehicle, the first message including a respective assessment for each proposed maneuver of at least two maneuvers proposed for the vehicle, and provide an in-vehicle instruction to perform the maneuver planned for the vehicle.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Rafael Rosales, Florian Geissler, Ignacio J. Alvarez, Neslihan Kose Cihangir
  • Voltage encoded MAC and bus scrambling
    Patent number: 11949793
    Abstract: Various embodiments are generally directed to providing authentication and confidentiality mechanisms for message communication over an in-vehicle network. For example, authentication data associated with a communicating node may be transmitted over the network by encoding different predefined voltage levels on top of the message bits of the message being communicated. Different voltage levels may represent different encodings, such as a bit-pair or any bit combination of the authentication data. In a further example, messaging confidentiality between at least two communicating nodes may be achieved by pseudo-randomly flipping, or scrambling, the dominant and recessive voltages of the entire message frame at the analog level based on a pseudo-random control bit sequence.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Marcio Juliato, Shabbir Ahmed, Christopher Gutierrez, Xiruo Liu, Manoj Sastry, Liuyang Yang
  • Compute optimizations for low precision machine learning operations
    Patent number: 11948224
    Abstract: One embodiment provides an apparatus comprising a memory stack including multiple memory dies and a parallel processor including a plurality of multiprocessors. Each multiprocessor has a single instruction, multiple thread (SIMT) architecture, the parallel processor coupled to the memory stack via one or more memory interfaces. At least one multiprocessor comprises a multiply-accumulate circuit to perform multiply-accumulate operations on matrix data in a stage of a neural network implementation to produce a result matrix comprising a plurality of matrix data elements at a first precision, precision tracking logic to evaluate metrics associated with the matrix data elements and indicate if an optimization is to be performed for representing data at a second stage of the neural network implementation, and a numerical transform unit to dynamically perform a numerical transform operation on the matrix data elements based on the indication to produce transformed matrix data elements at a second precision.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Anbang Yao, Kevin Nealis, Xiaoming Chen, Altug Koker, Abhishek R. Appu, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Ben J. Ashbaugh, Barath Lakshmanan, Liwei Ma, Joydeep Ray, Ping T. Tang, Michael S. Strickland
  • Mechanisms for transmission of multiple downlink control information
    Patent number: 11950267
    Abstract: The disclosure provides mechanisms for transmission of multiple DCIs. An apparatus for an AN includes RF interface circuitry; and processing circuitry coupled with the interface circuitry and configured to: multiplex one or more PDCCHs carrying DCI for a UE in a TDM manner; perform a resource mapping to map the multiplexed one or more PDCCHs into frequency and time resources in a CORESET; and provide the multiplexed one or more PDCCHs to the RF interface circuitry for transmission to the UE with the frequency and time resources in the CORESET.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Dae Won Lee, Yingyang Li, Gang Xiong
  • Video feature tagging
    Patent number: 11948392
    Abstract: An activity recording system is provided. The activity recording system includes a three-dimensional camera, a sensor arrangement that is fitted to a subject being recorded, and an activity recording device. The activity recording device receives image information from the three-dimensional camera and sensor arrangement information from the sensor arrangement. Both the image information and the sensor arrangement information include location measurements. The sensor arrangement information is generated by location sensors that are positioned at target features of the subject to be tracked. The sensor arrangement information is a key to the image information that specifies where, in any given image, the target features of the subject lie. Activity data having these characteristics may be applied to solve a variety of system development problems. Such activity data can be used to training machine learning components or test computer vision components for a fraction of the cost of using conventional techniques.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventor: Amit Bleiweiss
  • Memory architecture with shared bitline at back-end-of-line
    Patent number: 11950407
    Abstract: Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Juan G. Alzate Vinasco, Travis W. Lajoie, Abhishek A. Sharma, Kimberly L Pierce, Elliot N. Tan, Yu-Jin Chen, Van H. Le, Pei-Hua Wang, Bernhard Sell
  • Apparatus with multi-wafer based device and method for forming such
    Patent number: 11948831
    Abstract: An apparatus is provided which comprises: a substrate; one or more active devices adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Anup Pancholi, Prashant Majhi, Paul Fischer, Patrick Morrow
  • System and method for adapting executable object to a processing unit
    Patent number: 11947977
    Abstract: Embodiments are generally directed to a system and method for adapting executable object to a processing unit. An embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: April 2, 2024
    Assignee: INTEL CORPORATION
    Inventors: Li Xu, Haihao Xiang, Feng Chen, Travis Schluessler, Yuheng Zhang, Sen Lin
  • Methods and apparatus to process commands from virtual machines
    Patent number: 11947991
    Abstract: A disclosed example includes accessing, by a backend block service driver in an input/output virtual machine executing on one or more processors, a first command submitted to a buffer by a paravirtualized input/output frontend block driver executing in a guest virtual machine; generating, by the backend block service driver, a translated command based on the first command by translating a virtual parameter of the first command to a physical parameter associated with a physical resource; submitting, by the backend block service driver, the translated command to an input/output queue to be processed by the physical resource based on the physical parameter; and submitting, by the backend block service driver, a completion status entry to the buffer, the completion status entry indicative of completion of a direct memory access operation that copies data between the physical resource and a guest memory buffer corresponding to the guest virtual machine.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Yao Zu Dong, Yuankai Guo, Haozhong Zhang, Kun Tian
  • Detecting objects in video frames using similarity detectors
    Patent number: 11948340
    Abstract: An example apparatus for detecting objects in video frames includes a receiver to receive a plurality of video frames from a video camera. The apparatus also includes a first still image object detector to receive a first frame of the plurality of video frames and calculate localization information and confidence information for each potential object patch in the first frame. The apparatus further includes a second still image object detector to receive an adjacent frame of the plurality of video frames adjacent to the first frame and calculate localization information and confidence information for each potential object patch in the adjacent frame. The apparatus includes a similarity detector trained to detect paired patches between the first frame and the adjacent frame based on a comparison of the detected potential object patches.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Kun Yu, Ciyong Chen, Xiaotian Guo, Yan Hao, Hui Li, Lu Li, Jianguo Pei, Zhi Yong Zhu
  • Thread modification to reduce command conversion latency
    Patent number: 11948017
    Abstract: Examples described herein relate to a graphics processing apparatus that includes a memory device; and a central processing unit (CPU). In some examples, the CPU is configured to: execute a producer to issue graphics command application program interfaces (APIs); execute a driver to translate graphics command APIs into executable instructions; and based on an idle state of the producer, execute a command translation code segment of the producer to translate graphics command APIs into executable instructions. In some examples, the execution unit is coupled to the memory device, the execution unit to execute one or more of the executable instructions. In some examples, the producer includes multiple portions such as application code, graphics pipeline runtime code, and command translation code segment.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek Venkatesh, Michael Apodaca, Stav Gurtovoy, John H. Feit, Mateusz Przybylski, David M. Cimini
  • Die over mold stacked semiconductor package
    Patent number: 11948917
    Abstract: Embodiments described herein provide a semiconductor package comprising multiple dies encapsulated in multiple molding compounds. In one example, a semiconductor package comprises: a first die or die stack on a substrate; a first molding compound encapsulating the first die or die stack on the substrate; a second die or die stack on the first molding compound; and a second molding compound encapsulating the second die or die stack and at least one portion of the first molding compound. In this example, the first die or die stack is electrically coupled to the substrate using a first wire bond and the second die or die stack is electrically coupled to the substrate using a second wire bond. Additionally, the first molding compound encapsulates the first wire bond and the second molding compound encapsulates the second wire bond. Furthermore, a footprint of the second die overlaps a footprint of the first die.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Florence Pon, Yi Xu, James Zhang, Yuhong Cai, Tyler Leuten, William Glennan, Hyoung Il Kim
  • Vertically spaced intra-level interconnect line metallization for integrated circuit devices
    Patent number: 11948874
    Abstract: An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Sukru Yemenicioglu, Patrick Morrow, Richard Schenker, Mauro Kobrinsky
  • Methods, apparatus, and articles of manufacture to improve in-memory multiply and accumulate operations
    Patent number: 11949414
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve in-memory multiply and accumulate operations. An example apparatus includes a first multiplexer in a subarray of memory, the first multiplexer to receive first values representative of a column of a lookup table (LUT) including entries to represent products of four-bit numbers and return second values from an intersection of a row and the column of the LUT based on a first element of a first operand; shift and adder logic in the subarray, the shift and adder logic to shift the second values based on at least one of the first element of the first operand or a first element of a second operand; and accumulation storage in the subarray, the accumulation storage to store at least the shifted second values.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: April 2, 2024
    Assignee: INTEL CORPORATION
    Inventors: Gurpreet Singh Kalsi, Akshay Krishna Ramanathan, Kamlesh Pillai, Sreenivas Subramoney, Srivatsa Rangachar Srinivasa, Anirud Thyagharajan, Om Ji Omer, Saurabh Jain
  • Coil for mobile device context-driven switching and wireless charging
    Patent number: 11949170
    Abstract: Apparatus, system and method to provide switchable coils in a computing device, comprising: a plurality of electrically conductive coils to transfer electromagnetic energy; a sensor coupled to a processor, to select a coil from among the plurality of electrically conductive coils; a switch to energize the selected coil; and a switch controller coupled to the switch and to the processor. In some embodiments, the plurality of coils may comprise an inductive charging interface. Some embodiments may further include a communication interface between the processor to the plurality of electrically conductive coils, the plurality of coils comprising an interface for near-field communications (NFC). The antenna coils may be arranged to provide improved NFC coverage when the computing device is in a respective predetermined physical configuration. Sensors may be used to detect the configuration and switch NFC communications to use a preferred antenna coil for the detected configuration.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Anand S. Konanur, Songnan Yang, Ulun Karacaoglu, Jiancheng Tao, Farid Adrangi
  • Hybrid backside thermal structures for enhanced IC packages
    Patent number: 11948906
    Abstract: An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Feras Eid, Joe Walczyk, Weihua Tang, Akhilesh Rallabandi, Marco Aurelio Cartas Ayala
  • Transformer, transmitter circuit, semiconductor chip, semiconductor package, base station, mobile device, and method for a radio frequency transmitter
    Patent number: 11949446
    Abstract: The present disclosure relates to a concept for a transformer, a transmitter circuit, a semiconductor chip, a semiconductor package, a base station, a mobile device and a method for a radio frequency transmitter. The transformer for a radio frequency transmitter circuit comprises a primary coil and a secondary coils, which are configured to receive an input signal and to provide an output signal, and a ternary coil configured to provide a feedback signal.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Daniel Gruber, Mark Elzinga, Martin Clara
  • Mechanism to provide visual feedback regarding computing system command gestures
    Patent number: 11941181
    Abstract: A mechanism to provide visual feedback regarding computing system command gestures. An embodiment of an apparatus includes a sensing element to sense a presence or movement of a user of the apparatus, a processor, wherein operation of the processor includes interpretation of command gestures of a user to provide input to the apparatus; and a display screen, the apparatus to display one or more icons on the display screen, the one or more icons being related to the operation of the apparatus. The apparatus is to display visual feedback for a user of the apparatus, visual feedback including a representation of one or both hands of the user while the one or both hands are within a sensing area for the sensing element.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: March 26, 2024
    Assignee: Intel Corporation
    Inventors: Rajiv Mongia, Achintya Bhowmik, Mark Yahiro, Dana Krieger, Ed Mangum, Diana Povieng
  • Computer with a wrap around display
    Patent number: D1020731
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventor: David M. Collins